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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v | FileCheck %s3; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR154; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v,+unaligned-vector-mem | FileCheck %s --check-prefix=UNALIGNED_VEC_MEM5 6define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.ptr, ptr %add.ptr64) {7; CHECK-LABEL: define i32 @test(8; CHECK-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: entry:10; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[PIX1]], i64 411; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 412; CHECK-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]13; CHECK-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]14; CHECK-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 415; CHECK-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 416; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]17; CHECK-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]18; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 419; CHECK-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 420; CHECK-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 421; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 122; CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr null, align 123; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PIX1]], align 124; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>25; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PIX2]], align 126; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>27; CHECK-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP3]], [[TMP5]]28; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[TMP1]], align 129; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>30; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 131; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i32>32; CHECK-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP8]], [[TMP10]]33; CHECK-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP11]], splat (i32 16)34; CHECK-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP6]]35; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>36; CHECK-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP13]]37; CHECK-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP14]], [[TMP13]]38; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP15]], <4 x i32> [[TMP16]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>39; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>40; CHECK-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]41; CHECK-NEXT: [[TMP20:%.*]] = sub <4 x i32> [[TMP17]], [[TMP18]]42; CHECK-NEXT: [[TMP88:%.*]] = shufflevector <4 x i32> [[TMP19]], <4 x i32> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>43; CHECK-NEXT: [[TMP22:%.*]] = load <4 x i8>, ptr [[ADD_PTR3]], align 144; CHECK-NEXT: [[TMP23:%.*]] = zext <4 x i8> [[TMP22]] to <4 x i32>45; CHECK-NEXT: [[TMP24:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 146; CHECK-NEXT: [[TMP25:%.*]] = zext <4 x i8> [[TMP24]] to <4 x i32>47; CHECK-NEXT: [[TMP26:%.*]] = sub <4 x i32> [[TMP23]], [[TMP25]]48; CHECK-NEXT: [[TMP27:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 149; CHECK-NEXT: [[TMP28:%.*]] = zext <4 x i8> [[TMP27]] to <4 x i32>50; CHECK-NEXT: [[TMP29:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 151; CHECK-NEXT: [[TMP30:%.*]] = zext <4 x i8> [[TMP29]] to <4 x i32>52; CHECK-NEXT: [[TMP31:%.*]] = sub <4 x i32> [[TMP28]], [[TMP30]]53; CHECK-NEXT: [[TMP32:%.*]] = shl <4 x i32> [[TMP31]], splat (i32 16)54; CHECK-NEXT: [[TMP33:%.*]] = add <4 x i32> [[TMP32]], [[TMP26]]55; CHECK-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP33]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>56; CHECK-NEXT: [[TMP35:%.*]] = add <4 x i32> [[TMP34]], [[TMP33]]57; CHECK-NEXT: [[TMP36:%.*]] = sub <4 x i32> [[TMP34]], [[TMP33]]58; CHECK-NEXT: [[TMP37:%.*]] = shufflevector <4 x i32> [[TMP35]], <4 x i32> [[TMP36]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>59; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>60; CHECK-NEXT: [[TMP39:%.*]] = add <4 x i32> [[TMP37]], [[TMP38]]61; CHECK-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP37]], [[TMP38]]62; CHECK-NEXT: [[TMP89:%.*]] = shufflevector <4 x i32> [[TMP39]], <4 x i32> [[TMP40]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>63; CHECK-NEXT: [[TMP42:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 164; CHECK-NEXT: [[TMP43:%.*]] = zext <4 x i8> [[TMP42]] to <4 x i32>65; CHECK-NEXT: [[TMP44:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 166; CHECK-NEXT: [[TMP45:%.*]] = zext <4 x i8> [[TMP44]] to <4 x i32>67; CHECK-NEXT: [[TMP46:%.*]] = sub <4 x i32> [[TMP43]], [[TMP45]]68; CHECK-NEXT: [[TMP47:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 169; CHECK-NEXT: [[TMP48:%.*]] = zext <4 x i8> [[TMP47]] to <4 x i32>70; CHECK-NEXT: [[TMP49:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 171; CHECK-NEXT: [[TMP50:%.*]] = zext <4 x i8> [[TMP49]] to <4 x i32>72; CHECK-NEXT: [[TMP51:%.*]] = sub <4 x i32> [[TMP48]], [[TMP50]]73; CHECK-NEXT: [[TMP52:%.*]] = shl <4 x i32> [[TMP51]], splat (i32 16)74; CHECK-NEXT: [[TMP53:%.*]] = add <4 x i32> [[TMP52]], [[TMP46]]75; CHECK-NEXT: [[TMP54:%.*]] = shufflevector <4 x i32> [[TMP53]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>76; CHECK-NEXT: [[TMP55:%.*]] = add <4 x i32> [[TMP54]], [[TMP53]]77; CHECK-NEXT: [[TMP56:%.*]] = sub <4 x i32> [[TMP54]], [[TMP53]]78; CHECK-NEXT: [[TMP57:%.*]] = shufflevector <4 x i32> [[TMP55]], <4 x i32> [[TMP56]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>79; CHECK-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>80; CHECK-NEXT: [[TMP59:%.*]] = add <4 x i32> [[TMP57]], [[TMP58]]81; CHECK-NEXT: [[TMP60:%.*]] = sub <4 x i32> [[TMP57]], [[TMP58]]82; CHECK-NEXT: [[TMP61:%.*]] = shufflevector <4 x i32> [[TMP59]], <4 x i32> [[TMP60]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>83; CHECK-NEXT: [[TMP62:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)84; CHECK-NEXT: [[TMP63:%.*]] = load <4 x i8>, ptr null, align 185; CHECK-NEXT: [[TMP64:%.*]] = zext <4 x i8> [[TMP63]] to <4 x i32>86; CHECK-NEXT: [[TMP65:%.*]] = load <4 x i8>, ptr null, align 187; CHECK-NEXT: [[TMP66:%.*]] = zext <4 x i8> [[TMP65]] to <4 x i32>88; CHECK-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]89; CHECK-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>90; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i8> poison, i8 [[TMP115]], i32 091; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i8> [[TMP69]], i8 [[TMP0]], i32 192; CHECK-NEXT: [[TMP117:%.*]] = shufflevector <2 x i8> [[TMP62]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>93; CHECK-NEXT: [[TMP71:%.*]] = shufflevector <4 x i8> [[TMP70]], <4 x i8> [[TMP117]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>94; CHECK-NEXT: [[TMP72:%.*]] = zext <4 x i8> [[TMP71]] to <4 x i32>95; CHECK-NEXT: [[TMP73:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 196; CHECK-NEXT: [[TMP74:%.*]] = zext <4 x i8> [[TMP73]] to <4 x i32>97; CHECK-NEXT: [[TMP75:%.*]] = shufflevector <4 x i32> [[TMP74]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>98; CHECK-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP72]], [[TMP75]]99; CHECK-NEXT: [[TMP77:%.*]] = shl <4 x i32> [[TMP76]], splat (i32 16)100; CHECK-NEXT: [[TMP78:%.*]] = add <4 x i32> [[TMP77]], [[TMP68]]101; CHECK-NEXT: [[TMP79:%.*]] = shufflevector <4 x i32> [[TMP78]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>102; CHECK-NEXT: [[TMP80:%.*]] = add <4 x i32> [[TMP78]], [[TMP79]]103; CHECK-NEXT: [[TMP81:%.*]] = sub <4 x i32> [[TMP78]], [[TMP79]]104; CHECK-NEXT: [[TMP82:%.*]] = shufflevector <4 x i32> [[TMP80]], <4 x i32> [[TMP81]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>105; CHECK-NEXT: [[TMP83:%.*]] = shufflevector <4 x i32> [[TMP82]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>106; CHECK-NEXT: [[TMP84:%.*]] = add <4 x i32> [[TMP82]], [[TMP83]]107; CHECK-NEXT: [[TMP85:%.*]] = sub <4 x i32> [[TMP82]], [[TMP83]]108; CHECK-NEXT: [[TMP86:%.*]] = shufflevector <4 x i32> [[TMP84]], <4 x i32> [[TMP85]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>109; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <4 x i32> [[TMP89]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>110; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP88]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>111; CHECK-NEXT: [[TMP87:%.*]] = add <4 x i32> [[TMP41]], [[TMP21]]112; CHECK-NEXT: [[TMP106:%.*]] = sub <4 x i32> [[TMP88]], [[TMP89]]113; CHECK-NEXT: [[TMP90:%.*]] = shufflevector <4 x i32> [[TMP106]], <4 x i32> [[TMP87]], <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>114; CHECK-NEXT: [[TMP91:%.*]] = add <4 x i32> [[TMP86]], [[TMP61]]115; CHECK-NEXT: [[TMP92:%.*]] = sub <4 x i32> [[TMP61]], [[TMP86]]116; CHECK-NEXT: [[TMP93:%.*]] = shufflevector <4 x i32> [[TMP92]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>117; CHECK-NEXT: [[TMP118:%.*]] = shufflevector <4 x i32> [[TMP91]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>118; CHECK-NEXT: [[TMP94:%.*]] = shufflevector <8 x i32> [[TMP93]], <8 x i32> [[TMP118]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>119; CHECK-NEXT: [[TMP95:%.*]] = add <8 x i32> [[TMP94]], [[TMP90]]120; CHECK-NEXT: [[TMP96:%.*]] = sub <8 x i32> [[TMP90]], [[TMP94]]121; CHECK-NEXT: [[TMP97:%.*]] = shufflevector <8 x i32> [[TMP95]], <8 x i32> [[TMP96]], <16 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7, i32 12, i32 8, i32 13, i32 9, i32 14, i32 10, i32 15, i32 11>122; CHECK-NEXT: [[TMP98:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> [[TMP64]], <16 x i32> <i32 2, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>123; CHECK-NEXT: [[TMP99:%.*]] = shufflevector <4 x i32> [[TMP43]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>124; CHECK-NEXT: [[TMP100:%.*]] = shufflevector <16 x i32> [[TMP98]], <16 x i32> [[TMP99]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>125; CHECK-NEXT: [[TMP101:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>126; CHECK-NEXT: [[TMP102:%.*]] = shufflevector <16 x i32> [[TMP100]], <16 x i32> [[TMP101]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 poison, i32 poison, i32 poison>127; CHECK-NEXT: [[TMP103:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>128; CHECK-NEXT: [[TMP104:%.*]] = shufflevector <16 x i32> [[TMP102]], <16 x i32> [[TMP103]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 poison, i32 18, i32 19>129; CHECK-NEXT: [[TMP105:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>130; CHECK-NEXT: [[TMP116:%.*]] = shufflevector <16 x i32> [[TMP104]], <16 x i32> [[TMP105]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 18, i32 poison, i32 19, i32 poison, i32 12, i32 poison, i32 14, i32 15>131; CHECK-NEXT: [[TMP107:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>132; CHECK-NEXT: [[TMP108:%.*]] = shufflevector <16 x i32> [[TMP116]], <16 x i32> [[TMP107]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 18, i32 10, i32 19, i32 12, i32 16, i32 14, i32 15>133; CHECK-NEXT: [[TMP109:%.*]] = lshr <16 x i32> [[TMP108]], splat (i32 15)134; CHECK-NEXT: [[TMP110:%.*]] = and <16 x i32> [[TMP109]], splat (i32 65537)135; CHECK-NEXT: [[TMP111:%.*]] = mul <16 x i32> [[TMP110]], splat (i32 65535)136; CHECK-NEXT: [[TMP112:%.*]] = add <16 x i32> [[TMP111]], [[TMP97]]137; CHECK-NEXT: [[TMP113:%.*]] = xor <16 x i32> [[TMP112]], [[TMP108]]138; CHECK-NEXT: [[TMP114:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP113]])139; CHECK-NEXT: ret i32 [[TMP114]]140;141; THR15-LABEL: define i32 @test(142; THR15-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {143; THR15-NEXT: entry:144; THR15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4145; THR15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4146; THR15-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]147; THR15-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]148; THR15-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4149; THR15-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4150; THR15-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]151; THR15-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]152; THR15-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4153; THR15-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4154; THR15-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4155; THR15-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1156; THR15-NEXT: [[TMP1:%.*]] = load i8, ptr null, align 1157; THR15-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PIX1]], align 1158; THR15-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>159; THR15-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1160; THR15-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>161; THR15-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP3]], [[TMP5]]162; THR15-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3]], align 1163; THR15-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>164; THR15-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1165; THR15-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i32>166; THR15-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP8]], [[TMP10]]167; THR15-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP11]], splat (i32 16)168; THR15-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP6]]169; THR15-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>170; THR15-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP13]]171; THR15-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP14]], [[TMP13]]172; THR15-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP15]], <4 x i32> [[TMP16]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>173; THR15-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>174; THR15-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]175; THR15-NEXT: [[TMP20:%.*]] = sub <4 x i32> [[TMP17]], [[TMP18]]176; THR15-NEXT: [[TMP88:%.*]] = shufflevector <4 x i32> [[TMP19]], <4 x i32> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>177; THR15-NEXT: [[TMP22:%.*]] = load <4 x i8>, ptr [[ADD_PTR3]], align 1178; THR15-NEXT: [[TMP23:%.*]] = zext <4 x i8> [[TMP22]] to <4 x i32>179; THR15-NEXT: [[TMP24:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1180; THR15-NEXT: [[TMP25:%.*]] = zext <4 x i8> [[TMP24]] to <4 x i32>181; THR15-NEXT: [[TMP26:%.*]] = sub <4 x i32> [[TMP23]], [[TMP25]]182; THR15-NEXT: [[TMP27:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1183; THR15-NEXT: [[TMP28:%.*]] = zext <4 x i8> [[TMP27]] to <4 x i32>184; THR15-NEXT: [[TMP29:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1185; THR15-NEXT: [[TMP30:%.*]] = zext <4 x i8> [[TMP29]] to <4 x i32>186; THR15-NEXT: [[TMP31:%.*]] = sub <4 x i32> [[TMP28]], [[TMP30]]187; THR15-NEXT: [[TMP32:%.*]] = shl <4 x i32> [[TMP31]], splat (i32 16)188; THR15-NEXT: [[TMP33:%.*]] = add <4 x i32> [[TMP32]], [[TMP26]]189; THR15-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP33]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>190; THR15-NEXT: [[TMP35:%.*]] = add <4 x i32> [[TMP34]], [[TMP33]]191; THR15-NEXT: [[TMP36:%.*]] = sub <4 x i32> [[TMP34]], [[TMP33]]192; THR15-NEXT: [[TMP37:%.*]] = shufflevector <4 x i32> [[TMP35]], <4 x i32> [[TMP36]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>193; THR15-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>194; THR15-NEXT: [[TMP39:%.*]] = add <4 x i32> [[TMP37]], [[TMP38]]195; THR15-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP37]], [[TMP38]]196; THR15-NEXT: [[TMP89:%.*]] = shufflevector <4 x i32> [[TMP39]], <4 x i32> [[TMP40]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>197; THR15-NEXT: [[TMP42:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1198; THR15-NEXT: [[TMP43:%.*]] = zext <4 x i8> [[TMP42]] to <4 x i32>199; THR15-NEXT: [[TMP44:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1200; THR15-NEXT: [[TMP45:%.*]] = zext <4 x i8> [[TMP44]] to <4 x i32>201; THR15-NEXT: [[TMP46:%.*]] = sub <4 x i32> [[TMP43]], [[TMP45]]202; THR15-NEXT: [[TMP47:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1203; THR15-NEXT: [[TMP48:%.*]] = zext <4 x i8> [[TMP47]] to <4 x i32>204; THR15-NEXT: [[TMP49:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1205; THR15-NEXT: [[TMP50:%.*]] = zext <4 x i8> [[TMP49]] to <4 x i32>206; THR15-NEXT: [[TMP51:%.*]] = sub <4 x i32> [[TMP48]], [[TMP50]]207; THR15-NEXT: [[TMP52:%.*]] = shl <4 x i32> [[TMP51]], splat (i32 16)208; THR15-NEXT: [[TMP53:%.*]] = add <4 x i32> [[TMP52]], [[TMP46]]209; THR15-NEXT: [[TMP54:%.*]] = shufflevector <4 x i32> [[TMP53]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>210; THR15-NEXT: [[TMP55:%.*]] = add <4 x i32> [[TMP54]], [[TMP53]]211; THR15-NEXT: [[TMP56:%.*]] = sub <4 x i32> [[TMP54]], [[TMP53]]212; THR15-NEXT: [[TMP57:%.*]] = shufflevector <4 x i32> [[TMP55]], <4 x i32> [[TMP56]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>213; THR15-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>214; THR15-NEXT: [[TMP59:%.*]] = add <4 x i32> [[TMP57]], [[TMP58]]215; THR15-NEXT: [[TMP60:%.*]] = sub <4 x i32> [[TMP57]], [[TMP58]]216; THR15-NEXT: [[TMP61:%.*]] = shufflevector <4 x i32> [[TMP59]], <4 x i32> [[TMP60]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>217; THR15-NEXT: [[TMP62:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)218; THR15-NEXT: [[TMP63:%.*]] = load <4 x i8>, ptr null, align 1219; THR15-NEXT: [[TMP64:%.*]] = zext <4 x i8> [[TMP63]] to <4 x i32>220; THR15-NEXT: [[TMP65:%.*]] = load <4 x i8>, ptr null, align 1221; THR15-NEXT: [[TMP66:%.*]] = zext <4 x i8> [[TMP65]] to <4 x i32>222; THR15-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]223; THR15-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>224; THR15-NEXT: [[TMP69:%.*]] = insertelement <4 x i8> poison, i8 [[TMP1]], i32 0225; THR15-NEXT: [[TMP70:%.*]] = insertelement <4 x i8> [[TMP69]], i8 [[TMP0]], i32 1226; THR15-NEXT: [[TMP116:%.*]] = shufflevector <2 x i8> [[TMP62]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>227; THR15-NEXT: [[TMP71:%.*]] = shufflevector <4 x i8> [[TMP70]], <4 x i8> [[TMP116]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>228; THR15-NEXT: [[TMP72:%.*]] = zext <4 x i8> [[TMP71]] to <4 x i32>229; THR15-NEXT: [[TMP73:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 1230; THR15-NEXT: [[TMP74:%.*]] = zext <4 x i8> [[TMP73]] to <4 x i32>231; THR15-NEXT: [[TMP75:%.*]] = shufflevector <4 x i32> [[TMP74]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>232; THR15-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP72]], [[TMP75]]233; THR15-NEXT: [[TMP77:%.*]] = shl <4 x i32> [[TMP76]], splat (i32 16)234; THR15-NEXT: [[TMP78:%.*]] = add <4 x i32> [[TMP77]], [[TMP68]]235; THR15-NEXT: [[TMP79:%.*]] = shufflevector <4 x i32> [[TMP78]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>236; THR15-NEXT: [[TMP80:%.*]] = add <4 x i32> [[TMP78]], [[TMP79]]237; THR15-NEXT: [[TMP81:%.*]] = sub <4 x i32> [[TMP78]], [[TMP79]]238; THR15-NEXT: [[TMP82:%.*]] = shufflevector <4 x i32> [[TMP80]], <4 x i32> [[TMP81]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>239; THR15-NEXT: [[TMP83:%.*]] = shufflevector <4 x i32> [[TMP82]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>240; THR15-NEXT: [[TMP84:%.*]] = add <4 x i32> [[TMP82]], [[TMP83]]241; THR15-NEXT: [[TMP85:%.*]] = sub <4 x i32> [[TMP82]], [[TMP83]]242; THR15-NEXT: [[TMP86:%.*]] = shufflevector <4 x i32> [[TMP84]], <4 x i32> [[TMP85]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>243; THR15-NEXT: [[TMP41:%.*]] = shufflevector <4 x i32> [[TMP89]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>244; THR15-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP88]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>245; THR15-NEXT: [[TMP87:%.*]] = add <4 x i32> [[TMP41]], [[TMP21]]246; THR15-NEXT: [[TMP106:%.*]] = sub <4 x i32> [[TMP88]], [[TMP89]]247; THR15-NEXT: [[TMP90:%.*]] = shufflevector <4 x i32> [[TMP106]], <4 x i32> [[TMP87]], <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>248; THR15-NEXT: [[TMP91:%.*]] = add <4 x i32> [[TMP86]], [[TMP61]]249; THR15-NEXT: [[TMP92:%.*]] = sub <4 x i32> [[TMP61]], [[TMP86]]250; THR15-NEXT: [[TMP93:%.*]] = shufflevector <4 x i32> [[TMP92]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>251; THR15-NEXT: [[TMP117:%.*]] = shufflevector <4 x i32> [[TMP91]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>252; THR15-NEXT: [[TMP94:%.*]] = shufflevector <8 x i32> [[TMP93]], <8 x i32> [[TMP117]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>253; THR15-NEXT: [[TMP95:%.*]] = add <8 x i32> [[TMP94]], [[TMP90]]254; THR15-NEXT: [[TMP96:%.*]] = sub <8 x i32> [[TMP90]], [[TMP94]]255; THR15-NEXT: [[TMP97:%.*]] = shufflevector <8 x i32> [[TMP95]], <8 x i32> [[TMP96]], <16 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7, i32 12, i32 8, i32 13, i32 9, i32 14, i32 10, i32 15, i32 11>256; THR15-NEXT: [[TMP98:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> [[TMP64]], <16 x i32> <i32 2, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>257; THR15-NEXT: [[TMP99:%.*]] = shufflevector <4 x i32> [[TMP43]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>258; THR15-NEXT: [[TMP100:%.*]] = shufflevector <16 x i32> [[TMP98]], <16 x i32> [[TMP99]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>259; THR15-NEXT: [[TMP101:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>260; THR15-NEXT: [[TMP102:%.*]] = shufflevector <16 x i32> [[TMP100]], <16 x i32> [[TMP101]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 poison, i32 poison, i32 poison>261; THR15-NEXT: [[TMP103:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>262; THR15-NEXT: [[TMP104:%.*]] = shufflevector <16 x i32> [[TMP102]], <16 x i32> [[TMP103]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 poison, i32 18, i32 19>263; THR15-NEXT: [[TMP105:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>264; THR15-NEXT: [[TMP115:%.*]] = shufflevector <16 x i32> [[TMP104]], <16 x i32> [[TMP105]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 18, i32 poison, i32 19, i32 poison, i32 12, i32 poison, i32 14, i32 15>265; THR15-NEXT: [[TMP107:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>266; THR15-NEXT: [[TMP108:%.*]] = shufflevector <16 x i32> [[TMP115]], <16 x i32> [[TMP107]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 18, i32 10, i32 19, i32 12, i32 16, i32 14, i32 15>267; THR15-NEXT: [[TMP109:%.*]] = lshr <16 x i32> [[TMP108]], splat (i32 15)268; THR15-NEXT: [[TMP110:%.*]] = and <16 x i32> [[TMP109]], splat (i32 65537)269; THR15-NEXT: [[TMP111:%.*]] = mul <16 x i32> [[TMP110]], splat (i32 65535)270; THR15-NEXT: [[TMP112:%.*]] = add <16 x i32> [[TMP111]], [[TMP97]]271; THR15-NEXT: [[TMP113:%.*]] = xor <16 x i32> [[TMP112]], [[TMP108]]272; THR15-NEXT: [[TMP114:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP113]])273; THR15-NEXT: ret i32 [[TMP114]]274;275; UNALIGNED_VEC_MEM-LABEL: define i32 @test(276; UNALIGNED_VEC_MEM-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {277; UNALIGNED_VEC_MEM-NEXT: entry:278; UNALIGNED_VEC_MEM-NEXT: [[TMP54:%.*]] = load i8, ptr [[PIX1]], align 1279; UNALIGNED_VEC_MEM-NEXT: [[CONV:%.*]] = zext i8 [[TMP54]] to i32280; UNALIGNED_VEC_MEM-NEXT: [[TMP58:%.*]] = load i8, ptr [[PIX2]], align 1281; UNALIGNED_VEC_MEM-NEXT: [[CONV2:%.*]] = zext i8 [[TMP58]] to i32282; UNALIGNED_VEC_MEM-NEXT: [[SUB:%.*]] = sub i32 [[CONV]], [[CONV2]]283; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4284; UNALIGNED_VEC_MEM-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX3]], align 1285; UNALIGNED_VEC_MEM-NEXT: [[CONV4:%.*]] = zext i8 [[TMP2]] to i32286; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4287; UNALIGNED_VEC_MEM-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX5]], align 1288; UNALIGNED_VEC_MEM-NEXT: [[CONV6:%.*]] = zext i8 [[TMP3]] to i32289; UNALIGNED_VEC_MEM-NEXT: [[SUB7:%.*]] = sub i32 [[CONV4]], [[CONV6]]290; UNALIGNED_VEC_MEM-NEXT: [[SHL:%.*]] = shl i32 [[SUB7]], 16291; UNALIGNED_VEC_MEM-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[SUB]]292; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8:%.*]] = getelementptr i8, ptr [[PIX1]], i64 1293; UNALIGNED_VEC_MEM-NEXT: [[TMP4:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1294; UNALIGNED_VEC_MEM-NEXT: [[CONV9:%.*]] = zext i8 [[TMP4]] to i32295; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10:%.*]] = getelementptr i8, ptr [[PIX2]], i64 1296; UNALIGNED_VEC_MEM-NEXT: [[TMP5:%.*]] = load i8, ptr [[ARRAYIDX10]], align 1297; UNALIGNED_VEC_MEM-NEXT: [[CONV11:%.*]] = zext i8 [[TMP5]] to i32298; UNALIGNED_VEC_MEM-NEXT: [[SUB12:%.*]] = sub i32 [[CONV9]], [[CONV11]]299; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13:%.*]] = getelementptr i8, ptr [[PIX1]], i64 5300; UNALIGNED_VEC_MEM-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX13]], align 1301; UNALIGNED_VEC_MEM-NEXT: [[CONV14:%.*]] = zext i8 [[TMP6]] to i32302; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[PIX2]], i64 5303; UNALIGNED_VEC_MEM-NEXT: [[TMP7:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1304; UNALIGNED_VEC_MEM-NEXT: [[CONV16:%.*]] = zext i8 [[TMP7]] to i32305; UNALIGNED_VEC_MEM-NEXT: [[SUB17:%.*]] = sub i32 [[CONV14]], [[CONV16]]306; UNALIGNED_VEC_MEM-NEXT: [[SHL18:%.*]] = shl i32 [[SUB17]], 16307; UNALIGNED_VEC_MEM-NEXT: [[ADD19:%.*]] = add i32 [[SHL18]], [[SUB12]]308; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20:%.*]] = getelementptr i8, ptr [[PIX1]], i64 2309; UNALIGNED_VEC_MEM-NEXT: [[TMP8:%.*]] = load i8, ptr [[ARRAYIDX20]], align 1310; UNALIGNED_VEC_MEM-NEXT: [[CONV21:%.*]] = zext i8 [[TMP8]] to i32311; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22:%.*]] = getelementptr i8, ptr [[PIX2]], i64 2312; UNALIGNED_VEC_MEM-NEXT: [[TMP9:%.*]] = load i8, ptr [[ARRAYIDX22]], align 1313; UNALIGNED_VEC_MEM-NEXT: [[CONV23:%.*]] = zext i8 [[TMP9]] to i32314; UNALIGNED_VEC_MEM-NEXT: [[SUB24:%.*]] = sub i32 [[CONV21]], [[CONV23]]315; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25:%.*]] = getelementptr i8, ptr [[PIX1]], i64 6316; UNALIGNED_VEC_MEM-NEXT: [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX25]], align 1317; UNALIGNED_VEC_MEM-NEXT: [[CONV26:%.*]] = zext i8 [[TMP10]] to i32318; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27:%.*]] = getelementptr i8, ptr [[PIX2]], i64 6319; UNALIGNED_VEC_MEM-NEXT: [[TMP11:%.*]] = load i8, ptr [[ARRAYIDX27]], align 1320; UNALIGNED_VEC_MEM-NEXT: [[CONV28:%.*]] = zext i8 [[TMP11]] to i32321; UNALIGNED_VEC_MEM-NEXT: [[SUB29:%.*]] = sub i32 [[CONV26]], [[CONV28]]322; UNALIGNED_VEC_MEM-NEXT: [[SHL30:%.*]] = shl i32 [[SUB29]], 16323; UNALIGNED_VEC_MEM-NEXT: [[ADD31:%.*]] = add i32 [[SHL30]], [[SUB24]]324; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32:%.*]] = getelementptr i8, ptr [[PIX1]], i64 3325; UNALIGNED_VEC_MEM-NEXT: [[TMP12:%.*]] = load i8, ptr [[ARRAYIDX32]], align 1326; UNALIGNED_VEC_MEM-NEXT: [[CONV33:%.*]] = zext i8 [[TMP12]] to i32327; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34:%.*]] = getelementptr i8, ptr [[PIX2]], i64 3328; UNALIGNED_VEC_MEM-NEXT: [[TMP13:%.*]] = load i8, ptr [[ARRAYIDX34]], align 1329; UNALIGNED_VEC_MEM-NEXT: [[CONV35:%.*]] = zext i8 [[TMP13]] to i32330; UNALIGNED_VEC_MEM-NEXT: [[SUB36:%.*]] = sub i32 [[CONV33]], [[CONV35]]331; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37:%.*]] = getelementptr i8, ptr [[PIX1]], i64 7332; UNALIGNED_VEC_MEM-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX37]], align 1333; UNALIGNED_VEC_MEM-NEXT: [[CONV38:%.*]] = zext i8 [[TMP14]] to i32334; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39:%.*]] = getelementptr i8, ptr [[PIX2]], i64 7335; UNALIGNED_VEC_MEM-NEXT: [[TMP15:%.*]] = load i8, ptr [[ARRAYIDX39]], align 1336; UNALIGNED_VEC_MEM-NEXT: [[CONV40:%.*]] = zext i8 [[TMP15]] to i32337; UNALIGNED_VEC_MEM-NEXT: [[SUB41:%.*]] = sub i32 [[CONV38]], [[CONV40]]338; UNALIGNED_VEC_MEM-NEXT: [[SHL42:%.*]] = shl i32 [[SUB41]], 16339; UNALIGNED_VEC_MEM-NEXT: [[ADD43:%.*]] = add i32 [[SHL42]], [[SUB36]]340; UNALIGNED_VEC_MEM-NEXT: [[ADD44:%.*]] = add i32 [[ADD19]], [[ADD]]341; UNALIGNED_VEC_MEM-NEXT: [[SUB45:%.*]] = sub i32 [[ADD]], [[ADD19]]342; UNALIGNED_VEC_MEM-NEXT: [[ADD46:%.*]] = add i32 [[ADD43]], [[ADD31]]343; UNALIGNED_VEC_MEM-NEXT: [[SUB47:%.*]] = sub i32 [[ADD31]], [[ADD43]]344; UNALIGNED_VEC_MEM-NEXT: [[ADD48:%.*]] = add i32 [[ADD46]], [[ADD44]]345; UNALIGNED_VEC_MEM-NEXT: [[SUB51:%.*]] = sub i32 [[ADD44]], [[ADD46]]346; UNALIGNED_VEC_MEM-NEXT: [[ADD55:%.*]] = add i32 [[SUB47]], [[SUB45]]347; UNALIGNED_VEC_MEM-NEXT: [[SUB59:%.*]] = sub i32 [[SUB45]], [[SUB47]]348; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]349; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]350; UNALIGNED_VEC_MEM-NEXT: [[TMP16:%.*]] = load i8, ptr [[ADD_PTR3]], align 1351; UNALIGNED_VEC_MEM-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP16]] to i32352; UNALIGNED_VEC_MEM-NEXT: [[TMP17:%.*]] = load i8, ptr [[ADD_PTR644]], align 1353; UNALIGNED_VEC_MEM-NEXT: [[CONV2_1:%.*]] = zext i8 [[TMP17]] to i32354; UNALIGNED_VEC_MEM-NEXT: [[SUB_1:%.*]] = sub i32 [[CONV_1]], [[CONV2_1]]355; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4356; UNALIGNED_VEC_MEM-NEXT: [[TMP18:%.*]] = load i8, ptr [[ARRAYIDX3_1]], align 1357; UNALIGNED_VEC_MEM-NEXT: [[CONV4_1:%.*]] = zext i8 [[TMP18]] to i32358; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4359; UNALIGNED_VEC_MEM-NEXT: [[TMP19:%.*]] = load i8, ptr [[ARRAYIDX5_1]], align 1360; UNALIGNED_VEC_MEM-NEXT: [[CONV6_1:%.*]] = zext i8 [[TMP19]] to i32361; UNALIGNED_VEC_MEM-NEXT: [[SUB7_1:%.*]] = sub i32 [[CONV4_1]], [[CONV6_1]]362; UNALIGNED_VEC_MEM-NEXT: [[SHL_1:%.*]] = shl i32 [[SUB7_1]], 16363; UNALIGNED_VEC_MEM-NEXT: [[ADD_1:%.*]] = add i32 [[SHL_1]], [[SUB_1]]364; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 1365; UNALIGNED_VEC_MEM-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX8_1]], align 1366; UNALIGNED_VEC_MEM-NEXT: [[CONV9_1:%.*]] = zext i8 [[TMP20]] to i32367; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 1368; UNALIGNED_VEC_MEM-NEXT: [[TMP21:%.*]] = load i8, ptr [[ARRAYIDX10_1]], align 1369; UNALIGNED_VEC_MEM-NEXT: [[CONV11_1:%.*]] = zext i8 [[TMP21]] to i32370; UNALIGNED_VEC_MEM-NEXT: [[SUB12_1:%.*]] = sub i32 [[CONV9_1]], [[CONV11_1]]371; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 5372; UNALIGNED_VEC_MEM-NEXT: [[TMP22:%.*]] = load i8, ptr [[ARRAYIDX13_1]], align 1373; UNALIGNED_VEC_MEM-NEXT: [[CONV14_1:%.*]] = zext i8 [[TMP22]] to i32374; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 5375; UNALIGNED_VEC_MEM-NEXT: [[TMP23:%.*]] = load i8, ptr [[ARRAYIDX15_1]], align 1376; UNALIGNED_VEC_MEM-NEXT: [[CONV16_1:%.*]] = zext i8 [[TMP23]] to i32377; UNALIGNED_VEC_MEM-NEXT: [[SUB17_1:%.*]] = sub i32 [[CONV14_1]], [[CONV16_1]]378; UNALIGNED_VEC_MEM-NEXT: [[SHL18_1:%.*]] = shl i32 [[SUB17_1]], 16379; UNALIGNED_VEC_MEM-NEXT: [[ADD19_1:%.*]] = add i32 [[SHL18_1]], [[SUB12_1]]380; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 2381; UNALIGNED_VEC_MEM-NEXT: [[TMP24:%.*]] = load i8, ptr [[ARRAYIDX20_1]], align 1382; UNALIGNED_VEC_MEM-NEXT: [[CONV21_1:%.*]] = zext i8 [[TMP24]] to i32383; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 2384; UNALIGNED_VEC_MEM-NEXT: [[TMP25:%.*]] = load i8, ptr [[ARRAYIDX22_1]], align 1385; UNALIGNED_VEC_MEM-NEXT: [[CONV23_1:%.*]] = zext i8 [[TMP25]] to i32386; UNALIGNED_VEC_MEM-NEXT: [[SUB24_1:%.*]] = sub i32 [[CONV21_1]], [[CONV23_1]]387; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 6388; UNALIGNED_VEC_MEM-NEXT: [[TMP26:%.*]] = load i8, ptr [[ARRAYIDX25_1]], align 1389; UNALIGNED_VEC_MEM-NEXT: [[CONV26_1:%.*]] = zext i8 [[TMP26]] to i32390; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 6391; UNALIGNED_VEC_MEM-NEXT: [[TMP27:%.*]] = load i8, ptr [[ARRAYIDX27_1]], align 1392; UNALIGNED_VEC_MEM-NEXT: [[CONV28_1:%.*]] = zext i8 [[TMP27]] to i32393; UNALIGNED_VEC_MEM-NEXT: [[SUB29_1:%.*]] = sub i32 [[CONV26_1]], [[CONV28_1]]394; UNALIGNED_VEC_MEM-NEXT: [[SHL30_1:%.*]] = shl i32 [[SUB29_1]], 16395; UNALIGNED_VEC_MEM-NEXT: [[ADD31_1:%.*]] = add i32 [[SHL30_1]], [[SUB24_1]]396; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 3397; UNALIGNED_VEC_MEM-NEXT: [[TMP28:%.*]] = load i8, ptr [[ARRAYIDX32_1]], align 1398; UNALIGNED_VEC_MEM-NEXT: [[CONV33_1:%.*]] = zext i8 [[TMP28]] to i32399; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 3400; UNALIGNED_VEC_MEM-NEXT: [[TMP29:%.*]] = load i8, ptr [[ARRAYIDX34_1]], align 1401; UNALIGNED_VEC_MEM-NEXT: [[CONV35_1:%.*]] = zext i8 [[TMP29]] to i32402; UNALIGNED_VEC_MEM-NEXT: [[SUB36_1:%.*]] = sub i32 [[CONV33_1]], [[CONV35_1]]403; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 7404; UNALIGNED_VEC_MEM-NEXT: [[TMP30:%.*]] = load i8, ptr [[ARRAYIDX37_1]], align 1405; UNALIGNED_VEC_MEM-NEXT: [[CONV38_1:%.*]] = zext i8 [[TMP30]] to i32406; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 7407; UNALIGNED_VEC_MEM-NEXT: [[TMP31:%.*]] = load i8, ptr [[ARRAYIDX39_1]], align 1408; UNALIGNED_VEC_MEM-NEXT: [[CONV40_1:%.*]] = zext i8 [[TMP31]] to i32409; UNALIGNED_VEC_MEM-NEXT: [[SUB41_1:%.*]] = sub i32 [[CONV38_1]], [[CONV40_1]]410; UNALIGNED_VEC_MEM-NEXT: [[SHL42_1:%.*]] = shl i32 [[SUB41_1]], 16411; UNALIGNED_VEC_MEM-NEXT: [[ADD43_1:%.*]] = add i32 [[SHL42_1]], [[SUB36_1]]412; UNALIGNED_VEC_MEM-NEXT: [[ADD44_1:%.*]] = add i32 [[ADD19_1]], [[ADD_1]]413; UNALIGNED_VEC_MEM-NEXT: [[SUB45_1:%.*]] = sub i32 [[ADD_1]], [[ADD19_1]]414; UNALIGNED_VEC_MEM-NEXT: [[ADD46_1:%.*]] = add i32 [[ADD43_1]], [[ADD31_1]]415; UNALIGNED_VEC_MEM-NEXT: [[SUB47_1:%.*]] = sub i32 [[ADD31_1]], [[ADD43_1]]416; UNALIGNED_VEC_MEM-NEXT: [[ADD48_1:%.*]] = add i32 [[ADD46_1]], [[ADD44_1]]417; UNALIGNED_VEC_MEM-NEXT: [[SUB51_1:%.*]] = sub i32 [[ADD44_1]], [[ADD46_1]]418; UNALIGNED_VEC_MEM-NEXT: [[ADD55_1:%.*]] = add i32 [[SUB47_1]], [[SUB45_1]]419; UNALIGNED_VEC_MEM-NEXT: [[SUB59_1:%.*]] = sub i32 [[SUB45_1]], [[SUB47_1]]420; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]421; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]422; UNALIGNED_VEC_MEM-NEXT: [[TMP32:%.*]] = load i8, ptr [[ADD_PTR_1]], align 1423; UNALIGNED_VEC_MEM-NEXT: [[CONV_2:%.*]] = zext i8 [[TMP32]] to i32424; UNALIGNED_VEC_MEM-NEXT: [[TMP33:%.*]] = load i8, ptr [[ADD_PTR64_1]], align 1425; UNALIGNED_VEC_MEM-NEXT: [[CONV2_2:%.*]] = zext i8 [[TMP33]] to i32426; UNALIGNED_VEC_MEM-NEXT: [[SUB_2:%.*]] = sub i32 [[CONV_2]], [[CONV2_2]]427; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4428; UNALIGNED_VEC_MEM-NEXT: [[TMP34:%.*]] = load i8, ptr [[ARRAYIDX3_2]], align 1429; UNALIGNED_VEC_MEM-NEXT: [[CONV4_2:%.*]] = zext i8 [[TMP34]] to i32430; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4431; UNALIGNED_VEC_MEM-NEXT: [[TMP35:%.*]] = load i8, ptr [[ARRAYIDX5_2]], align 1432; UNALIGNED_VEC_MEM-NEXT: [[CONV6_2:%.*]] = zext i8 [[TMP35]] to i32433; UNALIGNED_VEC_MEM-NEXT: [[SUB7_2:%.*]] = sub i32 [[CONV4_2]], [[CONV6_2]]434; UNALIGNED_VEC_MEM-NEXT: [[SHL_2:%.*]] = shl i32 [[SUB7_2]], 16435; UNALIGNED_VEC_MEM-NEXT: [[ADD_2:%.*]] = add i32 [[SHL_2]], [[SUB_2]]436; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 1437; UNALIGNED_VEC_MEM-NEXT: [[TMP36:%.*]] = load i8, ptr [[ARRAYIDX8_2]], align 1438; UNALIGNED_VEC_MEM-NEXT: [[CONV9_2:%.*]] = zext i8 [[TMP36]] to i32439; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 1440; UNALIGNED_VEC_MEM-NEXT: [[TMP37:%.*]] = load i8, ptr [[ARRAYIDX10_2]], align 1441; UNALIGNED_VEC_MEM-NEXT: [[CONV11_2:%.*]] = zext i8 [[TMP37]] to i32442; UNALIGNED_VEC_MEM-NEXT: [[SUB12_2:%.*]] = sub i32 [[CONV9_2]], [[CONV11_2]]443; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 5444; UNALIGNED_VEC_MEM-NEXT: [[TMP38:%.*]] = load i8, ptr [[ARRAYIDX13_2]], align 1445; UNALIGNED_VEC_MEM-NEXT: [[CONV14_2:%.*]] = zext i8 [[TMP38]] to i32446; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 5447; UNALIGNED_VEC_MEM-NEXT: [[TMP39:%.*]] = load i8, ptr [[ARRAYIDX15_2]], align 1448; UNALIGNED_VEC_MEM-NEXT: [[CONV16_2:%.*]] = zext i8 [[TMP39]] to i32449; UNALIGNED_VEC_MEM-NEXT: [[SUB17_2:%.*]] = sub i32 [[CONV14_2]], [[CONV16_2]]450; UNALIGNED_VEC_MEM-NEXT: [[SHL18_2:%.*]] = shl i32 [[SUB17_2]], 16451; UNALIGNED_VEC_MEM-NEXT: [[ADD19_2:%.*]] = add i32 [[SHL18_2]], [[SUB12_2]]452; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 2453; UNALIGNED_VEC_MEM-NEXT: [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX20_2]], align 1454; UNALIGNED_VEC_MEM-NEXT: [[CONV21_2:%.*]] = zext i8 [[TMP40]] to i32455; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 2456; UNALIGNED_VEC_MEM-NEXT: [[TMP41:%.*]] = load i8, ptr [[ARRAYIDX22_2]], align 1457; UNALIGNED_VEC_MEM-NEXT: [[CONV23_2:%.*]] = zext i8 [[TMP41]] to i32458; UNALIGNED_VEC_MEM-NEXT: [[SUB24_2:%.*]] = sub i32 [[CONV21_2]], [[CONV23_2]]459; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 6460; UNALIGNED_VEC_MEM-NEXT: [[TMP42:%.*]] = load i8, ptr [[ARRAYIDX25_2]], align 1461; UNALIGNED_VEC_MEM-NEXT: [[CONV26_2:%.*]] = zext i8 [[TMP42]] to i32462; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 6463; UNALIGNED_VEC_MEM-NEXT: [[TMP43:%.*]] = load i8, ptr [[ARRAYIDX27_2]], align 1464; UNALIGNED_VEC_MEM-NEXT: [[CONV28_2:%.*]] = zext i8 [[TMP43]] to i32465; UNALIGNED_VEC_MEM-NEXT: [[SUB29_2:%.*]] = sub i32 [[CONV26_2]], [[CONV28_2]]466; UNALIGNED_VEC_MEM-NEXT: [[SHL30_2:%.*]] = shl i32 [[SUB29_2]], 16467; UNALIGNED_VEC_MEM-NEXT: [[ADD31_2:%.*]] = add i32 [[SHL30_2]], [[SUB24_2]]468; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 3469; UNALIGNED_VEC_MEM-NEXT: [[TMP44:%.*]] = load i8, ptr [[ARRAYIDX32_2]], align 1470; UNALIGNED_VEC_MEM-NEXT: [[CONV33_2:%.*]] = zext i8 [[TMP44]] to i32471; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 3472; UNALIGNED_VEC_MEM-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX34_2]], align 1473; UNALIGNED_VEC_MEM-NEXT: [[CONV35_2:%.*]] = zext i8 [[TMP45]] to i32474; UNALIGNED_VEC_MEM-NEXT: [[SUB36_2:%.*]] = sub i32 [[CONV33_2]], [[CONV35_2]]475; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 7476; UNALIGNED_VEC_MEM-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX37_2]], align 1477; UNALIGNED_VEC_MEM-NEXT: [[CONV38_2:%.*]] = zext i8 [[TMP46]] to i32478; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 7479; UNALIGNED_VEC_MEM-NEXT: [[TMP47:%.*]] = load i8, ptr [[ARRAYIDX39_2]], align 1480; UNALIGNED_VEC_MEM-NEXT: [[CONV40_2:%.*]] = zext i8 [[TMP47]] to i32481; UNALIGNED_VEC_MEM-NEXT: [[SUB41_2:%.*]] = sub i32 [[CONV38_2]], [[CONV40_2]]482; UNALIGNED_VEC_MEM-NEXT: [[SHL42_2:%.*]] = shl i32 [[SUB41_2]], 16483; UNALIGNED_VEC_MEM-NEXT: [[ADD43_2:%.*]] = add i32 [[SHL42_2]], [[SUB36_2]]484; UNALIGNED_VEC_MEM-NEXT: [[ADD44_2:%.*]] = add i32 [[ADD19_2]], [[ADD_2]]485; UNALIGNED_VEC_MEM-NEXT: [[SUB45_2:%.*]] = sub i32 [[ADD_2]], [[ADD19_2]]486; UNALIGNED_VEC_MEM-NEXT: [[ADD46_2:%.*]] = add i32 [[ADD43_2]], [[ADD31_2]]487; UNALIGNED_VEC_MEM-NEXT: [[SUB47_2:%.*]] = sub i32 [[ADD31_2]], [[ADD43_2]]488; UNALIGNED_VEC_MEM-NEXT: [[ADD48_2:%.*]] = add i32 [[ADD46_2]], [[ADD44_2]]489; UNALIGNED_VEC_MEM-NEXT: [[SUB51_2:%.*]] = sub i32 [[ADD44_2]], [[ADD46_2]]490; UNALIGNED_VEC_MEM-NEXT: [[ADD55_2:%.*]] = add i32 [[SUB47_2]], [[SUB45_2]]491; UNALIGNED_VEC_MEM-NEXT: [[SUB59_2:%.*]] = sub i32 [[SUB45_2]], [[SUB47_2]]492; UNALIGNED_VEC_MEM-NEXT: [[TMP48:%.*]] = load i8, ptr null, align 1493; UNALIGNED_VEC_MEM-NEXT: [[CONV_3:%.*]] = zext i8 [[TMP48]] to i32494; UNALIGNED_VEC_MEM-NEXT: [[TMP49:%.*]] = load i8, ptr null, align 1495; UNALIGNED_VEC_MEM-NEXT: [[CONV2_3:%.*]] = zext i8 [[TMP49]] to i32496; UNALIGNED_VEC_MEM-NEXT: [[SUB_3:%.*]] = sub i32 [[CONV_3]], [[CONV2_3]]497; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4498; UNALIGNED_VEC_MEM-NEXT: [[TMP50:%.*]] = load i8, ptr [[ARRAYIDX5_3]], align 1499; UNALIGNED_VEC_MEM-NEXT: [[CONV4_3:%.*]] = zext i8 [[TMP50]] to i32500; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_4:%.*]] = getelementptr i8, ptr null, i64 4501; UNALIGNED_VEC_MEM-NEXT: [[TMP51:%.*]] = load i8, ptr [[ARRAYIDX5_4]], align 1502; UNALIGNED_VEC_MEM-NEXT: [[CONV6_3:%.*]] = zext i8 [[TMP51]] to i32503; UNALIGNED_VEC_MEM-NEXT: [[SUB7_3:%.*]] = sub i32 [[CONV4_3]], [[CONV6_3]]504; UNALIGNED_VEC_MEM-NEXT: [[SHL_3:%.*]] = shl i32 [[SUB7_3]], 16505; UNALIGNED_VEC_MEM-NEXT: [[ADD_3:%.*]] = add i32 [[SHL_3]], [[SUB_3]]506; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_3:%.*]] = getelementptr i8, ptr null, i64 1507; UNALIGNED_VEC_MEM-NEXT: [[TMP52:%.*]] = load i8, ptr [[ARRAYIDX8_3]], align 1508; UNALIGNED_VEC_MEM-NEXT: [[CONV9_3:%.*]] = zext i8 [[TMP52]] to i32509; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr i8, ptr null, i64 1510; UNALIGNED_VEC_MEM-NEXT: [[TMP53:%.*]] = load i8, ptr [[ARRAYIDX10_3]], align 1511; UNALIGNED_VEC_MEM-NEXT: [[CONV11_3:%.*]] = zext i8 [[TMP53]] to i32512; UNALIGNED_VEC_MEM-NEXT: [[SUB12_3:%.*]] = sub i32 [[CONV9_3]], [[CONV11_3]]513; UNALIGNED_VEC_MEM-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1514; UNALIGNED_VEC_MEM-NEXT: [[CONV14_3:%.*]] = zext i8 [[TMP0]] to i32515; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_3:%.*]] = getelementptr i8, ptr null, i64 5516; UNALIGNED_VEC_MEM-NEXT: [[TMP55:%.*]] = load i8, ptr [[ARRAYIDX15_3]], align 1517; UNALIGNED_VEC_MEM-NEXT: [[CONV16_3:%.*]] = zext i8 [[TMP55]] to i32518; UNALIGNED_VEC_MEM-NEXT: [[SUB17_3:%.*]] = sub i32 [[CONV14_3]], [[CONV16_3]]519; UNALIGNED_VEC_MEM-NEXT: [[SHL18_3:%.*]] = shl i32 [[SUB17_3]], 16520; UNALIGNED_VEC_MEM-NEXT: [[ADD19_3:%.*]] = add i32 [[SHL18_3]], [[SUB12_3]]521; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_3:%.*]] = getelementptr i8, ptr null, i64 2522; UNALIGNED_VEC_MEM-NEXT: [[TMP56:%.*]] = load i8, ptr [[ARRAYIDX20_3]], align 1523; UNALIGNED_VEC_MEM-NEXT: [[CONV21_3:%.*]] = zext i8 [[TMP56]] to i32524; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_3:%.*]] = getelementptr i8, ptr null, i64 2525; UNALIGNED_VEC_MEM-NEXT: [[TMP57:%.*]] = load i8, ptr [[ARRAYIDX22_3]], align 1526; UNALIGNED_VEC_MEM-NEXT: [[CONV23_3:%.*]] = zext i8 [[TMP57]] to i32527; UNALIGNED_VEC_MEM-NEXT: [[SUB24_3:%.*]] = sub i32 [[CONV21_3]], [[CONV23_3]]528; UNALIGNED_VEC_MEM-NEXT: [[TMP1:%.*]] = load i8, ptr null, align 1529; UNALIGNED_VEC_MEM-NEXT: [[CONV26_3:%.*]] = zext i8 [[TMP1]] to i32530; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_3:%.*]] = getelementptr i8, ptr null, i64 6531; UNALIGNED_VEC_MEM-NEXT: [[TMP59:%.*]] = load i8, ptr [[ARRAYIDX27_3]], align 1532; UNALIGNED_VEC_MEM-NEXT: [[CONV28_3:%.*]] = zext i8 [[TMP59]] to i32533; UNALIGNED_VEC_MEM-NEXT: [[SUB29_3:%.*]] = sub i32 [[CONV26_3]], [[CONV28_3]]534; UNALIGNED_VEC_MEM-NEXT: [[SHL30_3:%.*]] = shl i32 [[SUB29_3]], 16535; UNALIGNED_VEC_MEM-NEXT: [[ADD31_3:%.*]] = add i32 [[SHL30_3]], [[SUB24_3]]536; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_3:%.*]] = getelementptr i8, ptr null, i64 3537; UNALIGNED_VEC_MEM-NEXT: [[TMP60:%.*]] = load i8, ptr [[ARRAYIDX32_3]], align 1538; UNALIGNED_VEC_MEM-NEXT: [[CONV33_3:%.*]] = zext i8 [[TMP60]] to i32539; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_3:%.*]] = getelementptr i8, ptr null, i64 3540; UNALIGNED_VEC_MEM-NEXT: [[TMP61:%.*]] = load i8, ptr [[ARRAYIDX34_3]], align 1541; UNALIGNED_VEC_MEM-NEXT: [[CONV35_3:%.*]] = zext i8 [[TMP61]] to i32542; UNALIGNED_VEC_MEM-NEXT: [[SUB36_3:%.*]] = sub i32 [[CONV33_3]], [[CONV35_3]]543; UNALIGNED_VEC_MEM-NEXT: [[TMP62:%.*]] = load i8, ptr null, align 1544; UNALIGNED_VEC_MEM-NEXT: [[CONV38_3:%.*]] = zext i8 [[TMP62]] to i32545; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_3:%.*]] = getelementptr i8, ptr null, i64 7546; UNALIGNED_VEC_MEM-NEXT: [[TMP63:%.*]] = load i8, ptr [[ARRAYIDX39_3]], align 1547; UNALIGNED_VEC_MEM-NEXT: [[CONV40_3:%.*]] = zext i8 [[TMP63]] to i32548; UNALIGNED_VEC_MEM-NEXT: [[SUB41_3:%.*]] = sub i32 [[CONV38_3]], [[CONV40_3]]549; UNALIGNED_VEC_MEM-NEXT: [[SHL42_3:%.*]] = shl i32 [[SUB41_3]], 16550; UNALIGNED_VEC_MEM-NEXT: [[ADD43_3:%.*]] = add i32 [[SHL42_3]], [[SUB36_3]]551; UNALIGNED_VEC_MEM-NEXT: [[ADD44_3:%.*]] = add i32 [[ADD19_3]], [[ADD_3]]552; UNALIGNED_VEC_MEM-NEXT: [[SUB45_3:%.*]] = sub i32 [[ADD_3]], [[ADD19_3]]553; UNALIGNED_VEC_MEM-NEXT: [[ADD46_3:%.*]] = add i32 [[ADD43_3]], [[ADD31_3]]554; UNALIGNED_VEC_MEM-NEXT: [[SUB47_3:%.*]] = sub i32 [[ADD31_3]], [[ADD43_3]]555; UNALIGNED_VEC_MEM-NEXT: [[ADD48_3:%.*]] = add i32 [[ADD46_3]], [[ADD44_3]]556; UNALIGNED_VEC_MEM-NEXT: [[SUB51_3:%.*]] = sub i32 [[ADD44_3]], [[ADD46_3]]557; UNALIGNED_VEC_MEM-NEXT: [[ADD55_3:%.*]] = add i32 [[SUB47_3]], [[SUB45_3]]558; UNALIGNED_VEC_MEM-NEXT: [[SUB59_3:%.*]] = sub i32 [[SUB45_3]], [[SUB47_3]]559; UNALIGNED_VEC_MEM-NEXT: [[ADD78:%.*]] = add i32 [[ADD48_1]], [[ADD48]]560; UNALIGNED_VEC_MEM-NEXT: [[SUB86:%.*]] = sub i32 [[ADD48]], [[ADD48_1]]561; UNALIGNED_VEC_MEM-NEXT: [[ADD94:%.*]] = add i32 [[ADD48_3]], [[ADD48_2]]562; UNALIGNED_VEC_MEM-NEXT: [[SUB102:%.*]] = sub i32 [[ADD48_2]], [[ADD48_3]]563; UNALIGNED_VEC_MEM-NEXT: [[ADD103:%.*]] = add i32 [[ADD94]], [[ADD78]]564; UNALIGNED_VEC_MEM-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD94]]565; UNALIGNED_VEC_MEM-NEXT: [[ADD105:%.*]] = add i32 [[SUB102]], [[SUB86]]566; UNALIGNED_VEC_MEM-NEXT: [[SUB106:%.*]] = sub i32 [[SUB86]], [[SUB102]]567; UNALIGNED_VEC_MEM-NEXT: [[SHR_I:%.*]] = lshr i32 [[CONV_3]], 15568; UNALIGNED_VEC_MEM-NEXT: [[AND_I:%.*]] = and i32 [[SHR_I]], 65537569; UNALIGNED_VEC_MEM-NEXT: [[MUL_I:%.*]] = mul i32 [[AND_I]], 65535570; UNALIGNED_VEC_MEM-NEXT: [[ADD_I:%.*]] = add i32 [[MUL_I]], [[ADD103]]571; UNALIGNED_VEC_MEM-NEXT: [[XOR_I:%.*]] = xor i32 [[ADD_I]], [[CONV_3]]572; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49:%.*]] = lshr i32 [[ADD46_2]], 15573; UNALIGNED_VEC_MEM-NEXT: [[AND_I50:%.*]] = and i32 [[SHR_I49]], 65537574; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51:%.*]] = mul i32 [[AND_I50]], 65535575; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52:%.*]] = add i32 [[MUL_I51]], [[ADD105]]576; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53:%.*]] = xor i32 [[ADD_I52]], [[ADD46_2]]577; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54:%.*]] = lshr i32 [[ADD46_1]], 15578; UNALIGNED_VEC_MEM-NEXT: [[AND_I55:%.*]] = and i32 [[SHR_I54]], 65537579; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56:%.*]] = mul i32 [[AND_I55]], 65535580; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57:%.*]] = add i32 [[MUL_I56]], [[SUB104]]581; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58:%.*]] = xor i32 [[ADD_I57]], [[ADD46_1]]582; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59:%.*]] = lshr i32 [[ADD46]], 15583; UNALIGNED_VEC_MEM-NEXT: [[AND_I60:%.*]] = and i32 [[SHR_I59]], 65537584; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61:%.*]] = mul i32 [[AND_I60]], 65535585; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62:%.*]] = add i32 [[MUL_I61]], [[SUB106]]586; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63:%.*]] = xor i32 [[ADD_I62]], [[ADD46]]587; UNALIGNED_VEC_MEM-NEXT: [[ADD110:%.*]] = add i32 [[XOR_I53]], [[XOR_I]]588; UNALIGNED_VEC_MEM-NEXT: [[ADD112:%.*]] = add i32 [[ADD110]], [[XOR_I58]]589; UNALIGNED_VEC_MEM-NEXT: [[ADD113:%.*]] = add i32 [[ADD112]], [[XOR_I63]]590; UNALIGNED_VEC_MEM-NEXT: [[ADD78_1:%.*]] = add i32 [[ADD55_1]], [[ADD55]]591; UNALIGNED_VEC_MEM-NEXT: [[SUB86_1:%.*]] = sub i32 [[ADD55]], [[ADD55_1]]592; UNALIGNED_VEC_MEM-NEXT: [[ADD94_1:%.*]] = add i32 [[ADD55_3]], [[ADD55_2]]593; UNALIGNED_VEC_MEM-NEXT: [[SUB102_1:%.*]] = sub i32 [[ADD55_2]], [[ADD55_3]]594; UNALIGNED_VEC_MEM-NEXT: [[ADD103_1:%.*]] = add i32 [[ADD94_1]], [[ADD78_1]]595; UNALIGNED_VEC_MEM-NEXT: [[SUB104_1:%.*]] = sub i32 [[ADD78_1]], [[ADD94_1]]596; UNALIGNED_VEC_MEM-NEXT: [[ADD105_1:%.*]] = add i32 [[SUB102_1]], [[SUB86_1]]597; UNALIGNED_VEC_MEM-NEXT: [[SUB106_1:%.*]] = sub i32 [[SUB86_1]], [[SUB102_1]]598; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_1:%.*]] = lshr i32 [[CONV9_2]], 15599; UNALIGNED_VEC_MEM-NEXT: [[AND_I_1:%.*]] = and i32 [[SHR_I_1]], 65537600; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_1:%.*]] = mul i32 [[AND_I_1]], 65535601; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_1:%.*]] = add i32 [[MUL_I_1]], [[ADD103_1]]602; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_1:%.*]] = xor i32 [[ADD_I_1]], [[CONV9_2]]603; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_1:%.*]] = lshr i32 [[CONV_2]], 15604; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_1:%.*]] = and i32 [[SHR_I49_1]], 65537605; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_1:%.*]] = mul i32 [[AND_I50_1]], 65535606; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_1:%.*]] = add i32 [[MUL_I51_1]], [[ADD105_1]]607; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_1:%.*]] = xor i32 [[ADD_I52_1]], [[CONV_2]]608; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_1:%.*]] = lshr i32 [[SUB47_1]], 15609; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_1:%.*]] = and i32 [[SHR_I54_1]], 65537610; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_1:%.*]] = mul i32 [[AND_I55_1]], 65535611; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_1:%.*]] = add i32 [[MUL_I56_1]], [[SUB104_1]]612; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_1:%.*]] = xor i32 [[ADD_I57_1]], [[SUB47_1]]613; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_1:%.*]] = lshr i32 [[SUB47]], 15614; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_1:%.*]] = and i32 [[SHR_I59_1]], 65537615; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_1:%.*]] = mul i32 [[AND_I60_1]], 65535616; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_1:%.*]] = add i32 [[MUL_I61_1]], [[SUB106_1]]617; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_1:%.*]] = xor i32 [[ADD_I62_1]], [[SUB47]]618; UNALIGNED_VEC_MEM-NEXT: [[ADD108_1:%.*]] = add i32 [[XOR_I53_1]], [[ADD113]]619; UNALIGNED_VEC_MEM-NEXT: [[ADD110_1:%.*]] = add i32 [[ADD108_1]], [[XOR_I_1]]620; UNALIGNED_VEC_MEM-NEXT: [[ADD112_1:%.*]] = add i32 [[ADD110_1]], [[XOR_I58_1]]621; UNALIGNED_VEC_MEM-NEXT: [[ADD113_1:%.*]] = add i32 [[ADD112_1]], [[XOR_I63_1]]622; UNALIGNED_VEC_MEM-NEXT: [[ADD78_2:%.*]] = add i32 [[SUB51_1]], [[SUB51]]623; UNALIGNED_VEC_MEM-NEXT: [[SUB86_2:%.*]] = sub i32 [[SUB51]], [[SUB51_1]]624; UNALIGNED_VEC_MEM-NEXT: [[ADD94_2:%.*]] = add i32 [[SUB51_3]], [[SUB51_2]]625; UNALIGNED_VEC_MEM-NEXT: [[SUB102_2:%.*]] = sub i32 [[SUB51_2]], [[SUB51_3]]626; UNALIGNED_VEC_MEM-NEXT: [[ADD103_2:%.*]] = add i32 [[ADD94_2]], [[ADD78_2]]627; UNALIGNED_VEC_MEM-NEXT: [[SUB104_2:%.*]] = sub i32 [[ADD78_2]], [[ADD94_2]]628; UNALIGNED_VEC_MEM-NEXT: [[ADD105_2:%.*]] = add i32 [[SUB102_2]], [[SUB86_2]]629; UNALIGNED_VEC_MEM-NEXT: [[SUB106_2:%.*]] = sub i32 [[SUB86_2]], [[SUB102_2]]630; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_2:%.*]] = lshr i32 [[CONV9_1]], 15631; UNALIGNED_VEC_MEM-NEXT: [[AND_I_2:%.*]] = and i32 [[SHR_I_2]], 65537632; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_2:%.*]] = mul i32 [[AND_I_2]], 65535633; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_2:%.*]] = add i32 [[MUL_I_2]], [[ADD103_2]]634; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_2:%.*]] = xor i32 [[ADD_I_2]], [[CONV9_1]]635; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_2:%.*]] = lshr i32 [[CONV_1]], 15636; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_2:%.*]] = and i32 [[SHR_I49_2]], 65537637; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_2:%.*]] = mul i32 [[AND_I50_2]], 65535638; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_2:%.*]] = add i32 [[MUL_I51_2]], [[ADD105_2]]639; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_2:%.*]] = xor i32 [[ADD_I52_2]], [[CONV_1]]640; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_2:%.*]] = lshr i32 [[CONV21_1]], 15641; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_2:%.*]] = and i32 [[SHR_I54_2]], 65537642; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_2:%.*]] = mul i32 [[AND_I55_2]], 65535643; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_2:%.*]] = add i32 [[MUL_I56_2]], [[SUB104_2]]644; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_2:%.*]] = xor i32 [[ADD_I57_2]], [[CONV21_1]]645; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_2:%.*]] = lshr i32 [[ADD44]], 15646; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_2:%.*]] = and i32 [[SHR_I59_2]], 65537647; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_2:%.*]] = mul i32 [[AND_I60_2]], 65535648; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_2:%.*]] = add i32 [[MUL_I61_2]], [[SUB106_2]]649; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_2:%.*]] = xor i32 [[ADD_I62_2]], [[ADD44]]650; UNALIGNED_VEC_MEM-NEXT: [[ADD108_2:%.*]] = add i32 [[XOR_I53_2]], [[ADD113_1]]651; UNALIGNED_VEC_MEM-NEXT: [[ADD110_2:%.*]] = add i32 [[ADD108_2]], [[XOR_I_2]]652; UNALIGNED_VEC_MEM-NEXT: [[ADD112_2:%.*]] = add i32 [[ADD110_2]], [[XOR_I58_2]]653; UNALIGNED_VEC_MEM-NEXT: [[ADD113_2:%.*]] = add i32 [[ADD112_2]], [[XOR_I63_2]]654; UNALIGNED_VEC_MEM-NEXT: [[ADD78_3:%.*]] = add i32 [[SUB59_1]], [[SUB59]]655; UNALIGNED_VEC_MEM-NEXT: [[SUB86_3:%.*]] = sub i32 [[SUB59]], [[SUB59_1]]656; UNALIGNED_VEC_MEM-NEXT: [[ADD94_3:%.*]] = add i32 [[SUB59_3]], [[SUB59_2]]657; UNALIGNED_VEC_MEM-NEXT: [[SUB102_3:%.*]] = sub i32 [[SUB59_2]], [[SUB59_3]]658; UNALIGNED_VEC_MEM-NEXT: [[ADD103_3:%.*]] = add i32 [[ADD94_3]], [[ADD78_3]]659; UNALIGNED_VEC_MEM-NEXT: [[SUB104_3:%.*]] = sub i32 [[ADD78_3]], [[ADD94_3]]660; UNALIGNED_VEC_MEM-NEXT: [[ADD105_3:%.*]] = add i32 [[SUB102_3]], [[SUB86_3]]661; UNALIGNED_VEC_MEM-NEXT: [[SUB106_3:%.*]] = sub i32 [[SUB86_3]], [[SUB102_3]]662; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_3:%.*]] = lshr i32 [[CONV9]], 15663; UNALIGNED_VEC_MEM-NEXT: [[AND_I_3:%.*]] = and i32 [[SHR_I_3]], 65537664; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_3:%.*]] = mul i32 [[AND_I_3]], 65535665; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_3:%.*]] = add i32 [[MUL_I_3]], [[ADD103_3]]666; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_3:%.*]] = xor i32 [[ADD_I_3]], [[CONV9]]667; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_3:%.*]] = lshr i32 [[CONV]], 15668; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_3:%.*]] = and i32 [[SHR_I49_3]], 65537669; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_3:%.*]] = mul i32 [[AND_I50_3]], 65535670; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_3:%.*]] = add i32 [[MUL_I51_3]], [[ADD105_3]]671; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_3:%.*]] = xor i32 [[ADD_I52_3]], [[CONV]]672; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_3:%.*]] = lshr i32 [[CONV21]], 15673; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_3:%.*]] = and i32 [[SHR_I54_3]], 65537674; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_3:%.*]] = mul i32 [[AND_I55_3]], 65535675; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_3:%.*]] = add i32 [[MUL_I56_3]], [[SUB104_3]]676; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_3:%.*]] = xor i32 [[ADD_I57_3]], [[CONV21]]677; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_3:%.*]] = lshr i32 [[CONV33]], 15678; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_3:%.*]] = and i32 [[SHR_I59_3]], 65537679; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_3:%.*]] = mul i32 [[AND_I60_3]], 65535680; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_3:%.*]] = add i32 [[MUL_I61_3]], [[SUB106_3]]681; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_3:%.*]] = xor i32 [[ADD_I62_3]], [[CONV33]]682; UNALIGNED_VEC_MEM-NEXT: [[ADD108_3:%.*]] = add i32 [[XOR_I53_3]], [[ADD113_2]]683; UNALIGNED_VEC_MEM-NEXT: [[ADD110_3:%.*]] = add i32 [[ADD108_3]], [[XOR_I_3]]684; UNALIGNED_VEC_MEM-NEXT: [[ADD112_3:%.*]] = add i32 [[ADD110_3]], [[XOR_I58_3]]685; UNALIGNED_VEC_MEM-NEXT: [[TMP117:%.*]] = add i32 [[ADD112_3]], [[XOR_I63_3]]686; UNALIGNED_VEC_MEM-NEXT: ret i32 [[TMP117]]687;688entry:689 %0 = load i8, ptr %pix1, align 1690 %conv = zext i8 %0 to i32691 %1 = load i8, ptr %pix2, align 1692 %conv2 = zext i8 %1 to i32693 %sub = sub i32 %conv, %conv2694 %arrayidx3 = getelementptr i8, ptr %pix1, i64 4695 %2 = load i8, ptr %arrayidx3, align 1696 %conv4 = zext i8 %2 to i32697 %arrayidx5 = getelementptr i8, ptr %pix2, i64 4698 %3 = load i8, ptr %arrayidx5, align 1699 %conv6 = zext i8 %3 to i32700 %sub7 = sub i32 %conv4, %conv6701 %shl = shl i32 %sub7, 16702 %add = add i32 %shl, %sub703 %arrayidx8 = getelementptr i8, ptr %pix1, i64 1704 %4 = load i8, ptr %arrayidx8, align 1705 %conv9 = zext i8 %4 to i32706 %arrayidx10 = getelementptr i8, ptr %pix2, i64 1707 %5 = load i8, ptr %arrayidx10, align 1708 %conv11 = zext i8 %5 to i32709 %sub12 = sub i32 %conv9, %conv11710 %arrayidx13 = getelementptr i8, ptr %pix1, i64 5711 %6 = load i8, ptr %arrayidx13, align 1712 %conv14 = zext i8 %6 to i32713 %arrayidx15 = getelementptr i8, ptr %pix2, i64 5714 %7 = load i8, ptr %arrayidx15, align 1715 %conv16 = zext i8 %7 to i32716 %sub17 = sub i32 %conv14, %conv16717 %shl18 = shl i32 %sub17, 16718 %add19 = add i32 %shl18, %sub12719 %arrayidx20 = getelementptr i8, ptr %pix1, i64 2720 %8 = load i8, ptr %arrayidx20, align 1721 %conv21 = zext i8 %8 to i32722 %arrayidx22 = getelementptr i8, ptr %pix2, i64 2723 %9 = load i8, ptr %arrayidx22, align 1724 %conv23 = zext i8 %9 to i32725 %sub24 = sub i32 %conv21, %conv23726 %arrayidx25 = getelementptr i8, ptr %pix1, i64 6727 %10 = load i8, ptr %arrayidx25, align 1728 %conv26 = zext i8 %10 to i32729 %arrayidx27 = getelementptr i8, ptr %pix2, i64 6730 %11 = load i8, ptr %arrayidx27, align 1731 %conv28 = zext i8 %11 to i32732 %sub29 = sub i32 %conv26, %conv28733 %shl30 = shl i32 %sub29, 16734 %add31 = add i32 %shl30, %sub24735 %arrayidx32 = getelementptr i8, ptr %pix1, i64 3736 %12 = load i8, ptr %arrayidx32, align 1737 %conv33 = zext i8 %12 to i32738 %arrayidx34 = getelementptr i8, ptr %pix2, i64 3739 %13 = load i8, ptr %arrayidx34, align 1740 %conv35 = zext i8 %13 to i32741 %sub36 = sub i32 %conv33, %conv35742 %arrayidx37 = getelementptr i8, ptr %pix1, i64 7743 %14 = load i8, ptr %arrayidx37, align 1744 %conv38 = zext i8 %14 to i32745 %arrayidx39 = getelementptr i8, ptr %pix2, i64 7746 %15 = load i8, ptr %arrayidx39, align 1747 %conv40 = zext i8 %15 to i32748 %sub41 = sub i32 %conv38, %conv40749 %shl42 = shl i32 %sub41, 16750 %add43 = add i32 %shl42, %sub36751 %add44 = add i32 %add19, %add752 %sub45 = sub i32 %add, %add19753 %add46 = add i32 %add43, %add31754 %sub47 = sub i32 %add31, %add43755 %add48 = add i32 %add46, %add44756 %sub51 = sub i32 %add44, %add46757 %add55 = add i32 %sub47, %sub45758 %sub59 = sub i32 %sub45, %sub47759 %add.ptr3 = getelementptr i8, ptr %pix1, i64 %idx.ext760 %add.ptr644 = getelementptr i8, ptr %pix2, i64 %idx.ext63761 %16 = load i8, ptr %add.ptr3, align 1762 %conv.1 = zext i8 %16 to i32763 %17 = load i8, ptr %add.ptr644, align 1764 %conv2.1 = zext i8 %17 to i32765 %sub.1 = sub i32 %conv.1, %conv2.1766 %arrayidx3.1 = getelementptr i8, ptr %add.ptr3, i64 4767 %18 = load i8, ptr %arrayidx3.1, align 1768 %conv4.1 = zext i8 %18 to i32769 %arrayidx5.1 = getelementptr i8, ptr %add.ptr644, i64 4770 %19 = load i8, ptr %arrayidx5.1, align 1771 %conv6.1 = zext i8 %19 to i32772 %sub7.1 = sub i32 %conv4.1, %conv6.1773 %shl.1 = shl i32 %sub7.1, 16774 %add.1 = add i32 %shl.1, %sub.1775 %arrayidx8.1 = getelementptr i8, ptr %add.ptr3, i64 1776 %20 = load i8, ptr %arrayidx8.1, align 1777 %conv9.1 = zext i8 %20 to i32778 %arrayidx10.1 = getelementptr i8, ptr %add.ptr644, i64 1779 %21 = load i8, ptr %arrayidx10.1, align 1780 %conv11.1 = zext i8 %21 to i32781 %sub12.1 = sub i32 %conv9.1, %conv11.1782 %arrayidx13.1 = getelementptr i8, ptr %add.ptr3, i64 5783 %22 = load i8, ptr %arrayidx13.1, align 1784 %conv14.1 = zext i8 %22 to i32785 %arrayidx15.1 = getelementptr i8, ptr %add.ptr644, i64 5786 %23 = load i8, ptr %arrayidx15.1, align 1787 %conv16.1 = zext i8 %23 to i32788 %sub17.1 = sub i32 %conv14.1, %conv16.1789 %shl18.1 = shl i32 %sub17.1, 16790 %add19.1 = add i32 %shl18.1, %sub12.1791 %arrayidx20.1 = getelementptr i8, ptr %add.ptr3, i64 2792 %24 = load i8, ptr %arrayidx20.1, align 1793 %conv21.1 = zext i8 %24 to i32794 %arrayidx22.1 = getelementptr i8, ptr %add.ptr644, i64 2795 %25 = load i8, ptr %arrayidx22.1, align 1796 %conv23.1 = zext i8 %25 to i32797 %sub24.1 = sub i32 %conv21.1, %conv23.1798 %arrayidx25.1 = getelementptr i8, ptr %add.ptr3, i64 6799 %26 = load i8, ptr %arrayidx25.1, align 1800 %conv26.1 = zext i8 %26 to i32801 %arrayidx27.1 = getelementptr i8, ptr %add.ptr644, i64 6802 %27 = load i8, ptr %arrayidx27.1, align 1803 %conv28.1 = zext i8 %27 to i32804 %sub29.1 = sub i32 %conv26.1, %conv28.1805 %shl30.1 = shl i32 %sub29.1, 16806 %add31.1 = add i32 %shl30.1, %sub24.1807 %arrayidx32.1 = getelementptr i8, ptr %add.ptr3, i64 3808 %28 = load i8, ptr %arrayidx32.1, align 1809 %conv33.1 = zext i8 %28 to i32810 %arrayidx34.1 = getelementptr i8, ptr %add.ptr644, i64 3811 %29 = load i8, ptr %arrayidx34.1, align 1812 %conv35.1 = zext i8 %29 to i32813 %sub36.1 = sub i32 %conv33.1, %conv35.1814 %arrayidx37.1 = getelementptr i8, ptr %add.ptr3, i64 7815 %30 = load i8, ptr %arrayidx37.1, align 1816 %conv38.1 = zext i8 %30 to i32817 %arrayidx39.1 = getelementptr i8, ptr %add.ptr644, i64 7818 %31 = load i8, ptr %arrayidx39.1, align 1819 %conv40.1 = zext i8 %31 to i32820 %sub41.1 = sub i32 %conv38.1, %conv40.1821 %shl42.1 = shl i32 %sub41.1, 16822 %add43.1 = add i32 %shl42.1, %sub36.1823 %add44.1 = add i32 %add19.1, %add.1824 %sub45.1 = sub i32 %add.1, %add19.1825 %add46.1 = add i32 %add43.1, %add31.1826 %sub47.1 = sub i32 %add31.1, %add43.1827 %add48.1 = add i32 %add46.1, %add44.1828 %sub51.1 = sub i32 %add44.1, %add46.1829 %add55.1 = add i32 %sub47.1, %sub45.1830 %sub59.1 = sub i32 %sub45.1, %sub47.1831 %add.ptr.1 = getelementptr i8, ptr %add.ptr, i64 %idx.ext832 %add.ptr64.1 = getelementptr i8, ptr %add.ptr64, i64 %idx.ext63833 %32 = load i8, ptr %add.ptr.1, align 1834 %conv.2 = zext i8 %32 to i32835 %33 = load i8, ptr %add.ptr64.1, align 1836 %conv2.2 = zext i8 %33 to i32837 %sub.2 = sub i32 %conv.2, %conv2.2838 %arrayidx3.2 = getelementptr i8, ptr %add.ptr.1, i64 4839 %34 = load i8, ptr %arrayidx3.2, align 1840 %conv4.2 = zext i8 %34 to i32841 %arrayidx5.2 = getelementptr i8, ptr %add.ptr64.1, i64 4842 %35 = load i8, ptr %arrayidx5.2, align 1843 %conv6.2 = zext i8 %35 to i32844 %sub7.2 = sub i32 %conv4.2, %conv6.2845 %shl.2 = shl i32 %sub7.2, 16846 %add.2 = add i32 %shl.2, %sub.2847 %arrayidx8.2 = getelementptr i8, ptr %add.ptr.1, i64 1848 %36 = load i8, ptr %arrayidx8.2, align 1849 %conv9.2 = zext i8 %36 to i32850 %arrayidx10.2 = getelementptr i8, ptr %add.ptr64.1, i64 1851 %37 = load i8, ptr %arrayidx10.2, align 1852 %conv11.2 = zext i8 %37 to i32853 %sub12.2 = sub i32 %conv9.2, %conv11.2854 %arrayidx13.2 = getelementptr i8, ptr %add.ptr.1, i64 5855 %38 = load i8, ptr %arrayidx13.2, align 1856 %conv14.2 = zext i8 %38 to i32857 %arrayidx15.2 = getelementptr i8, ptr %add.ptr64.1, i64 5858 %39 = load i8, ptr %arrayidx15.2, align 1859 %conv16.2 = zext i8 %39 to i32860 %sub17.2 = sub i32 %conv14.2, %conv16.2861 %shl18.2 = shl i32 %sub17.2, 16862 %add19.2 = add i32 %shl18.2, %sub12.2863 %arrayidx20.2 = getelementptr i8, ptr %add.ptr.1, i64 2864 %40 = load i8, ptr %arrayidx20.2, align 1865 %conv21.2 = zext i8 %40 to i32866 %arrayidx22.2 = getelementptr i8, ptr %add.ptr64.1, i64 2867 %41 = load i8, ptr %arrayidx22.2, align 1868 %conv23.2 = zext i8 %41 to i32869 %sub24.2 = sub i32 %conv21.2, %conv23.2870 %arrayidx25.2 = getelementptr i8, ptr %add.ptr.1, i64 6871 %42 = load i8, ptr %arrayidx25.2, align 1872 %conv26.2 = zext i8 %42 to i32873 %arrayidx27.2 = getelementptr i8, ptr %add.ptr64.1, i64 6874 %43 = load i8, ptr %arrayidx27.2, align 1875 %conv28.2 = zext i8 %43 to i32876 %sub29.2 = sub i32 %conv26.2, %conv28.2877 %shl30.2 = shl i32 %sub29.2, 16878 %add31.2 = add i32 %shl30.2, %sub24.2879 %arrayidx32.2 = getelementptr i8, ptr %add.ptr.1, i64 3880 %44 = load i8, ptr %arrayidx32.2, align 1881 %conv33.2 = zext i8 %44 to i32882 %arrayidx34.2 = getelementptr i8, ptr %add.ptr64.1, i64 3883 %45 = load i8, ptr %arrayidx34.2, align 1884 %conv35.2 = zext i8 %45 to i32885 %sub36.2 = sub i32 %conv33.2, %conv35.2886 %arrayidx37.2 = getelementptr i8, ptr %add.ptr.1, i64 7887 %46 = load i8, ptr %arrayidx37.2, align 1888 %conv38.2 = zext i8 %46 to i32889 %arrayidx39.2 = getelementptr i8, ptr %add.ptr64.1, i64 7890 %47 = load i8, ptr %arrayidx39.2, align 1891 %conv40.2 = zext i8 %47 to i32892 %sub41.2 = sub i32 %conv38.2, %conv40.2893 %shl42.2 = shl i32 %sub41.2, 16894 %add43.2 = add i32 %shl42.2, %sub36.2895 %add44.2 = add i32 %add19.2, %add.2896 %sub45.2 = sub i32 %add.2, %add19.2897 %add46.2 = add i32 %add43.2, %add31.2898 %sub47.2 = sub i32 %add31.2, %add43.2899 %add48.2 = add i32 %add46.2, %add44.2900 %sub51.2 = sub i32 %add44.2, %add46.2901 %add55.2 = add i32 %sub47.2, %sub45.2902 %sub59.2 = sub i32 %sub45.2, %sub47.2903 %48 = load i8, ptr null, align 1904 %conv.3 = zext i8 %48 to i32905 %49 = load i8, ptr null, align 1906 %conv2.3 = zext i8 %49 to i32907 %sub.3 = sub i32 %conv.3, %conv2.3908 %arrayidx3.3 = getelementptr i8, ptr null, i64 4909 %50 = load i8, ptr %arrayidx3.3, align 1910 %conv4.3 = zext i8 %50 to i32911 %arrayidx5.3 = getelementptr i8, ptr null, i64 4912 %51 = load i8, ptr %arrayidx5.3, align 1913 %conv6.3 = zext i8 %51 to i32914 %sub7.3 = sub i32 %conv4.3, %conv6.3915 %shl.3 = shl i32 %sub7.3, 16916 %add.3 = add i32 %shl.3, %sub.3917 %arrayidx8.3 = getelementptr i8, ptr null, i64 1918 %52 = load i8, ptr %arrayidx8.3, align 1919 %conv9.3 = zext i8 %52 to i32920 %arrayidx10.3 = getelementptr i8, ptr null, i64 1921 %53 = load i8, ptr %arrayidx10.3, align 1922 %conv11.3 = zext i8 %53 to i32923 %sub12.3 = sub i32 %conv9.3, %conv11.3924 %54 = load i8, ptr null, align 1925 %conv14.3 = zext i8 %54 to i32926 %arrayidx15.3 = getelementptr i8, ptr null, i64 5927 %55 = load i8, ptr %arrayidx15.3, align 1928 %conv16.3 = zext i8 %55 to i32929 %sub17.3 = sub i32 %conv14.3, %conv16.3930 %shl18.3 = shl i32 %sub17.3, 16931 %add19.3 = add i32 %shl18.3, %sub12.3932 %arrayidx20.3 = getelementptr i8, ptr null, i64 2933 %56 = load i8, ptr %arrayidx20.3, align 1934 %conv21.3 = zext i8 %56 to i32935 %arrayidx22.3 = getelementptr i8, ptr null, i64 2936 %57 = load i8, ptr %arrayidx22.3, align 1937 %conv23.3 = zext i8 %57 to i32938 %sub24.3 = sub i32 %conv21.3, %conv23.3939 %58 = load i8, ptr null, align 1940 %conv26.3 = zext i8 %58 to i32941 %arrayidx27.3 = getelementptr i8, ptr null, i64 6942 %59 = load i8, ptr %arrayidx27.3, align 1943 %conv28.3 = zext i8 %59 to i32944 %sub29.3 = sub i32 %conv26.3, %conv28.3945 %shl30.3 = shl i32 %sub29.3, 16946 %add31.3 = add i32 %shl30.3, %sub24.3947 %arrayidx32.3 = getelementptr i8, ptr null, i64 3948 %60 = load i8, ptr %arrayidx32.3, align 1949 %conv33.3 = zext i8 %60 to i32950 %arrayidx34.3 = getelementptr i8, ptr null, i64 3951 %61 = load i8, ptr %arrayidx34.3, align 1952 %conv35.3 = zext i8 %61 to i32953 %sub36.3 = sub i32 %conv33.3, %conv35.3954 %62 = load i8, ptr null, align 1955 %conv38.3 = zext i8 %62 to i32956 %arrayidx39.3 = getelementptr i8, ptr null, i64 7957 %63 = load i8, ptr %arrayidx39.3, align 1958 %conv40.3 = zext i8 %63 to i32959 %sub41.3 = sub i32 %conv38.3, %conv40.3960 %shl42.3 = shl i32 %sub41.3, 16961 %add43.3 = add i32 %shl42.3, %sub36.3962 %add44.3 = add i32 %add19.3, %add.3963 %sub45.3 = sub i32 %add.3, %add19.3964 %add46.3 = add i32 %add43.3, %add31.3965 %sub47.3 = sub i32 %add31.3, %add43.3966 %add48.3 = add i32 %add46.3, %add44.3967 %sub51.3 = sub i32 %add44.3, %add46.3968 %add55.3 = add i32 %sub47.3, %sub45.3969 %sub59.3 = sub i32 %sub45.3, %sub47.3970 %add78 = add i32 %add48.1, %add48971 %sub86 = sub i32 %add48, %add48.1972 %add94 = add i32 %add48.3, %add48.2973 %sub102 = sub i32 %add48.2, %add48.3974 %add103 = add i32 %add94, %add78975 %sub104 = sub i32 %add78, %add94976 %add105 = add i32 %sub102, %sub86977 %sub106 = sub i32 %sub86, %sub102978 %shr.i = lshr i32 %conv.3, 15979 %and.i = and i32 %shr.i, 65537980 %mul.i = mul i32 %and.i, 65535981 %add.i = add i32 %mul.i, %add103982 %xor.i = xor i32 %add.i, %conv.3983 %shr.i49 = lshr i32 %add46.2, 15984 %and.i50 = and i32 %shr.i49, 65537985 %mul.i51 = mul i32 %and.i50, 65535986 %add.i52 = add i32 %mul.i51, %add105987 %xor.i53 = xor i32 %add.i52, %add46.2988 %shr.i54 = lshr i32 %add46.1, 15989 %and.i55 = and i32 %shr.i54, 65537990 %mul.i56 = mul i32 %and.i55, 65535991 %add.i57 = add i32 %mul.i56, %sub104992 %xor.i58 = xor i32 %add.i57, %add46.1993 %shr.i59 = lshr i32 %add46, 15994 %and.i60 = and i32 %shr.i59, 65537995 %mul.i61 = mul i32 %and.i60, 65535996 %add.i62 = add i32 %mul.i61, %sub106997 %xor.i63 = xor i32 %add.i62, %add46998 %add110 = add i32 %xor.i53, %xor.i999 %add112 = add i32 %add110, %xor.i581000 %add113 = add i32 %add112, %xor.i631001 %add78.1 = add i32 %add55.1, %add551002 %sub86.1 = sub i32 %add55, %add55.11003 %add94.1 = add i32 %add55.3, %add55.21004 %sub102.1 = sub i32 %add55.2, %add55.31005 %add103.1 = add i32 %add94.1, %add78.11006 %sub104.1 = sub i32 %add78.1, %add94.11007 %add105.1 = add i32 %sub102.1, %sub86.11008 %sub106.1 = sub i32 %sub86.1, %sub102.11009 %shr.i.1 = lshr i32 %conv9.2, 151010 %and.i.1 = and i32 %shr.i.1, 655371011 %mul.i.1 = mul i32 %and.i.1, 655351012 %add.i.1 = add i32 %mul.i.1, %add103.11013 %xor.i.1 = xor i32 %add.i.1, %conv9.21014 %shr.i49.1 = lshr i32 %conv.2, 151015 %and.i50.1 = and i32 %shr.i49.1, 655371016 %mul.i51.1 = mul i32 %and.i50.1, 655351017 %add.i52.1 = add i32 %mul.i51.1, %add105.11018 %xor.i53.1 = xor i32 %add.i52.1, %conv.21019 %shr.i54.1 = lshr i32 %sub47.1, 151020 %and.i55.1 = and i32 %shr.i54.1, 655371021 %mul.i56.1 = mul i32 %and.i55.1, 655351022 %add.i57.1 = add i32 %mul.i56.1, %sub104.11023 %xor.i58.1 = xor i32 %add.i57.1, %sub47.11024 %shr.i59.1 = lshr i32 %sub47, 151025 %and.i60.1 = and i32 %shr.i59.1, 655371026 %mul.i61.1 = mul i32 %and.i60.1, 655351027 %add.i62.1 = add i32 %mul.i61.1, %sub106.11028 %xor.i63.1 = xor i32 %add.i62.1, %sub471029 %add108.1 = add i32 %xor.i53.1, %add1131030 %add110.1 = add i32 %add108.1, %xor.i.11031 %add112.1 = add i32 %add110.1, %xor.i58.11032 %add113.1 = add i32 %add112.1, %xor.i63.11033 %add78.2 = add i32 %sub51.1, %sub511034 %sub86.2 = sub i32 %sub51, %sub51.11035 %add94.2 = add i32 %sub51.3, %sub51.21036 %sub102.2 = sub i32 %sub51.2, %sub51.31037 %add103.2 = add i32 %add94.2, %add78.21038 %sub104.2 = sub i32 %add78.2, %add94.21039 %add105.2 = add i32 %sub102.2, %sub86.21040 %sub106.2 = sub i32 %sub86.2, %sub102.21041 %shr.i.2 = lshr i32 %conv9.1, 151042 %and.i.2 = and i32 %shr.i.2, 655371043 %mul.i.2 = mul i32 %and.i.2, 655351044 %add.i.2 = add i32 %mul.i.2, %add103.21045 %xor.i.2 = xor i32 %add.i.2, %conv9.11046 %shr.i49.2 = lshr i32 %conv.1, 151047 %and.i50.2 = and i32 %shr.i49.2, 655371048 %mul.i51.2 = mul i32 %and.i50.2, 655351049 %add.i52.2 = add i32 %mul.i51.2, %add105.21050 %xor.i53.2 = xor i32 %add.i52.2, %conv.11051 %shr.i54.2 = lshr i32 %conv21.1, 151052 %and.i55.2 = and i32 %shr.i54.2, 655371053 %mul.i56.2 = mul i32 %and.i55.2, 655351054 %add.i57.2 = add i32 %mul.i56.2, %sub104.21055 %xor.i58.2 = xor i32 %add.i57.2, %conv21.11056 %shr.i59.2 = lshr i32 %add44, 151057 %and.i60.2 = and i32 %shr.i59.2, 655371058 %mul.i61.2 = mul i32 %and.i60.2, 655351059 %add.i62.2 = add i32 %mul.i61.2, %sub106.21060 %xor.i63.2 = xor i32 %add.i62.2, %add441061 %add108.2 = add i32 %xor.i53.2, %add113.11062 %add110.2 = add i32 %add108.2, %xor.i.21063 %add112.2 = add i32 %add110.2, %xor.i58.21064 %add113.2 = add i32 %add112.2, %xor.i63.21065 %add78.3 = add i32 %sub59.1, %sub591066 %sub86.3 = sub i32 %sub59, %sub59.11067 %add94.3 = add i32 %sub59.3, %sub59.21068 %sub102.3 = sub i32 %sub59.2, %sub59.31069 %add103.3 = add i32 %add94.3, %add78.31070 %sub104.3 = sub i32 %add78.3, %add94.31071 %add105.3 = add i32 %sub102.3, %sub86.31072 %sub106.3 = sub i32 %sub86.3, %sub102.31073 %shr.i.3 = lshr i32 %conv9, 151074 %and.i.3 = and i32 %shr.i.3, 655371075 %mul.i.3 = mul i32 %and.i.3, 655351076 %add.i.3 = add i32 %mul.i.3, %add103.31077 %xor.i.3 = xor i32 %add.i.3, %conv91078 %shr.i49.3 = lshr i32 %conv, 151079 %and.i50.3 = and i32 %shr.i49.3, 655371080 %mul.i51.3 = mul i32 %and.i50.3, 655351081 %add.i52.3 = add i32 %mul.i51.3, %add105.31082 %xor.i53.3 = xor i32 %add.i52.3, %conv1083 %shr.i54.3 = lshr i32 %conv21, 151084 %and.i55.3 = and i32 %shr.i54.3, 655371085 %mul.i56.3 = mul i32 %and.i55.3, 655351086 %add.i57.3 = add i32 %mul.i56.3, %sub104.31087 %xor.i58.3 = xor i32 %add.i57.3, %conv211088 %shr.i59.3 = lshr i32 %conv33, 151089 %and.i60.3 = and i32 %shr.i59.3, 655371090 %mul.i61.3 = mul i32 %and.i60.3, 655351091 %add.i62.3 = add i32 %mul.i61.3, %sub106.31092 %xor.i63.3 = xor i32 %add.i62.3, %conv331093 %add108.3 = add i32 %xor.i53.3, %add113.21094 %add110.3 = add i32 %add108.3, %xor.i.31095 %add112.3 = add i32 %add110.3, %xor.i58.31096 %add113.3 = add i32 %add112.3, %xor.i63.31097 ret i32 %add113.31098}1099