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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+m,+v | FileCheck %s3; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+m,+v | FileCheck %s4; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+v,+zvbb | FileCheck %s5; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+v,+zvbb | FileCheck %s6 7define <4 x float> @rint_v4f32(ptr %a) {8; CHECK-LABEL: define <4 x float> @rint_v4f32(9; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: entry:11; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 1612; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[TMP0]])13; CHECK-NEXT: ret <4 x float> [[TMP1]]14;15entry:16 %0 = load <4 x float>, ptr %a17 %vecext = extractelement <4 x float> %0, i64 018 %1 = call float @llvm.rint.f32(float %vecext)19 %vecins = insertelement <4 x float> undef, float %1, i64 020 %vecext.1 = extractelement <4 x float> %0, i64 121 %2 = call float @llvm.rint.f32(float %vecext.1)22 %vecins.1 = insertelement <4 x float> %vecins, float %2, i64 123 %vecext.2 = extractelement <4 x float> %0, i64 224 %3 = call float @llvm.rint.f32(float %vecext.2)25 %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i64 226 %vecext.3 = extractelement <4 x float> %0, i64 327 %4 = call float @llvm.rint.f32(float %vecext.3)28 %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i64 329 ret <4 x float> %vecins.330}31 32define <2 x i32> @lrint_v2i32f32(ptr %a) {33; CHECK-LABEL: define <2 x i32> @lrint_v2i32f32(34; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {35; CHECK-NEXT: entry:36; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 837; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.lrint.v2i32.v2f32(<2 x float> [[TMP0]])38; CHECK-NEXT: ret <2 x i32> [[TMP1]]39;40entry:41 %0 = load <2 x float>, ptr %a42 %vecext = extractelement <2 x float> %0, i32 043 %1 = call i32 @llvm.lrint.i32.f32(float %vecext)44 %vecins = insertelement <2 x i32> undef, i32 %1, i32 045 %vecext.1 = extractelement <2 x float> %0, i32 146 %2 = call i32 @llvm.lrint.i32.f32(float %vecext.1)47 %vecins.1 = insertelement <2 x i32> %vecins, i32 %2, i32 148 ret <2 x i32> %vecins.149}50 51define <4 x i32> @lrint_v4i32f32(ptr %a) {52; CHECK-LABEL: define <4 x i32> @lrint_v4i32f32(53; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {54; CHECK-NEXT: entry:55; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 1656; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.lrint.v4i32.v4f32(<4 x float> [[TMP0]])57; CHECK-NEXT: ret <4 x i32> [[TMP1]]58;59entry:60 %0 = load <4 x float>, ptr %a61 %vecext = extractelement <4 x float> %0, i32 062 %1 = call i32 @llvm.lrint.i32.f32(float %vecext)63 %vecins = insertelement <4 x i32> undef, i32 %1, i32 064 %vecext.1 = extractelement <4 x float> %0, i32 165 %2 = call i32 @llvm.lrint.i32.f32(float %vecext.1)66 %vecins.1 = insertelement <4 x i32> %vecins, i32 %2, i32 167 %vecext.2 = extractelement <4 x float> %0, i32 268 %3 = call i32 @llvm.lrint.i32.f32(float %vecext.2)69 %vecins.2 = insertelement <4 x i32> %vecins.1, i32 %3, i32 270 %vecext.3 = extractelement <4 x float> %0, i32 371 %4 = call i32 @llvm.lrint.i32.f32(float %vecext.3)72 %vecins.3 = insertelement <4 x i32> %vecins.2, i32 %4, i32 373 ret <4 x i32> %vecins.374}75 76define <8 x i32> @lrint_v8i32f32(ptr %a) {77; CHECK-LABEL: define <8 x i32> @lrint_v8i32f32(78; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {79; CHECK-NEXT: entry:80; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[A]], align 3281; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.lrint.v8i32.v8f32(<8 x float> [[TMP0]])82; CHECK-NEXT: ret <8 x i32> [[TMP1]]83;84entry:85 %0 = load <8 x float>, ptr %a86 %vecext = extractelement <8 x float> %0, i32 087 %1 = call i32 @llvm.lrint.i32.f32(float %vecext)88 %vecins = insertelement <8 x i32> undef, i32 %1, i32 089 %vecext.1 = extractelement <8 x float> %0, i32 190 %2 = call i32 @llvm.lrint.i32.f32(float %vecext.1)91 %vecins.1 = insertelement <8 x i32> %vecins, i32 %2, i32 192 %vecext.2 = extractelement <8 x float> %0, i32 293 %3 = call i32 @llvm.lrint.i32.f32(float %vecext.2)94 %vecins.2 = insertelement <8 x i32> %vecins.1, i32 %3, i32 295 %vecext.3 = extractelement <8 x float> %0, i32 396 %4 = call i32 @llvm.lrint.i32.f32(float %vecext.3)97 %vecins.3 = insertelement <8 x i32> %vecins.2, i32 %4, i32 398 %vecext.4 = extractelement <8 x float> %0, i32 499 %5 = call i32 @llvm.lrint.i32.f32(float %vecext.4)100 %vecins.4 = insertelement <8 x i32> %vecins.3, i32 %5, i32 4101 %vecext.5 = extractelement <8 x float> %0, i32 5102 %6 = call i32 @llvm.lrint.i32.f32(float %vecext.5)103 %vecins.5 = insertelement <8 x i32> %vecins.4, i32 %6, i32 5104 %vecext.6 = extractelement <8 x float> %0, i32 6105 %7 = call i32 @llvm.lrint.i32.f32(float %vecext.6)106 %vecins.6 = insertelement <8 x i32> %vecins.5, i32 %7, i32 6107 %vecext.7 = extractelement <8 x float> %0, i32 7108 %8 = call i32 @llvm.lrint.i32.f32(float %vecext.7)109 %vecins.7 = insertelement <8 x i32> %vecins.6, i32 %8, i32 7110 ret <8 x i32> %vecins.7111}112 113define <2 x i64> @lrint_v2i64f32(ptr %a) {114; CHECK-LABEL: define <2 x i64> @lrint_v2i64f32(115; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {116; CHECK-NEXT: entry:117; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 8118; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float> [[TMP0]])119; CHECK-NEXT: ret <2 x i64> [[TMP1]]120;121entry:122 %0 = load <2 x float>, ptr %a123 %vecext = extractelement <2 x float> %0, i64 0124 %1 = call i64 @llvm.lrint.i64.f32(float %vecext)125 %vecins = insertelement <2 x i64> undef, i64 %1, i64 0126 %vecext.1 = extractelement <2 x float> %0, i64 1127 %2 = call i64 @llvm.lrint.i64.f32(float %vecext.1)128 %vecins.1 = insertelement <2 x i64> %vecins, i64 %2, i64 1129 ret <2 x i64> %vecins.1130}131 132define <4 x i64> @lrint_v4i64f32(ptr %a) {133; CHECK-LABEL: define <4 x i64> @lrint_v4i64f32(134; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {135; CHECK-NEXT: entry:136; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16137; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> [[TMP0]])138; CHECK-NEXT: ret <4 x i64> [[TMP1]]139;140entry:141 %0 = load <4 x float>, ptr %a142 %vecext = extractelement <4 x float> %0, i64 0143 %1 = call i64 @llvm.lrint.i64.f32(float %vecext)144 %vecins = insertelement <4 x i64> undef, i64 %1, i64 0145 %vecext.1 = extractelement <4 x float> %0, i64 1146 %2 = call i64 @llvm.lrint.i64.f32(float %vecext.1)147 %vecins.1 = insertelement <4 x i64> %vecins, i64 %2, i64 1148 %vecext.2 = extractelement <4 x float> %0, i64 2149 %3 = call i64 @llvm.lrint.i64.f32(float %vecext.2)150 %vecins.2 = insertelement <4 x i64> %vecins.1, i64 %3, i64 2151 %vecext.3 = extractelement <4 x float> %0, i64 3152 %4 = call i64 @llvm.lrint.i64.f32(float %vecext.3)153 %vecins.3 = insertelement <4 x i64> %vecins.2, i64 %4, i64 3154 ret <4 x i64> %vecins.3155}156 157define <8 x i64> @lrint_v8i64f32(ptr %a) {158; CHECK-LABEL: define <8 x i64> @lrint_v8i64f32(159; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {160; CHECK-NEXT: entry:161; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[A]], align 32162; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>163; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> [[TMP1]])164; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>165; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>166; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> [[TMP4]])167; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>168; CHECK-NEXT: [[VECINS_71:%.*]] = shufflevector <8 x i64> [[TMP3]], <8 x i64> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>169; CHECK-NEXT: ret <8 x i64> [[VECINS_71]]170;171entry:172 %0 = load <8 x float>, ptr %a173 %vecext = extractelement <8 x float> %0, i64 0174 %1 = call i64 @llvm.lrint.i64.f32(float %vecext)175 %vecins = insertelement <8 x i64> undef, i64 %1, i64 0176 %vecext.1 = extractelement <8 x float> %0, i64 1177 %2 = call i64 @llvm.lrint.i64.f32(float %vecext.1)178 %vecins.1 = insertelement <8 x i64> %vecins, i64 %2, i64 1179 %vecext.2 = extractelement <8 x float> %0, i64 2180 %3 = call i64 @llvm.lrint.i64.f32(float %vecext.2)181 %vecins.2 = insertelement <8 x i64> %vecins.1, i64 %3, i64 2182 %vecext.3 = extractelement <8 x float> %0, i64 3183 %4 = call i64 @llvm.lrint.i64.f32(float %vecext.3)184 %vecins.3 = insertelement <8 x i64> %vecins.2, i64 %4, i64 3185 %vecext.4 = extractelement <8 x float> %0, i64 4186 %5 = call i64 @llvm.lrint.i64.f32(float %vecext.4)187 %vecins.4 = insertelement <8 x i64> %vecins.3, i64 %5, i64 4188 %vecext.5 = extractelement <8 x float> %0, i64 5189 %6 = call i64 @llvm.lrint.i64.f32(float %vecext.5)190 %vecins.5 = insertelement <8 x i64> %vecins.4, i64 %6, i64 5191 %vecext.6 = extractelement <8 x float> %0, i64 6192 %7 = call i64 @llvm.lrint.i64.f32(float %vecext.6)193 %vecins.6 = insertelement <8 x i64> %vecins.5, i64 %7, i64 6194 %vecext.7 = extractelement <8 x float> %0, i64 7195 %8 = call i64 @llvm.lrint.i64.f32(float %vecext.7)196 %vecins.7 = insertelement <8 x i64> %vecins.6, i64 %8, i64 7197 ret <8 x i64> %vecins.7198}199 200define <2 x i64> @llrint_v2i64f32(ptr %a) {201; CHECK-LABEL: define <2 x i64> @llrint_v2i64f32(202; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {203; CHECK-NEXT: entry:204; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 8205; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> [[TMP0]])206; CHECK-NEXT: ret <2 x i64> [[TMP1]]207;208entry:209 %0 = load <2 x float>, ptr %a210 %vecext = extractelement <2 x float> %0, i64 0211 %1 = call i64 @llvm.llrint.i64.f32(float %vecext)212 %vecins = insertelement <2 x i64> undef, i64 %1, i64 0213 %vecext.1 = extractelement <2 x float> %0, i64 1214 %2 = call i64 @llvm.llrint.i64.f32(float %vecext.1)215 %vecins.1 = insertelement <2 x i64> %vecins, i64 %2, i64 1216 ret <2 x i64> %vecins.1217}218 219define <4 x i64> @llrint_v4i64f32(ptr %a) {220; CHECK-LABEL: define <4 x i64> @llrint_v4i64f32(221; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {222; CHECK-NEXT: entry:223; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16224; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> [[TMP0]])225; CHECK-NEXT: ret <4 x i64> [[TMP1]]226;227entry:228 %0 = load <4 x float>, ptr %a229 %vecext = extractelement <4 x float> %0, i64 0230 %1 = call i64 @llvm.llrint.i64.f32(float %vecext)231 %vecins = insertelement <4 x i64> undef, i64 %1, i64 0232 %vecext.1 = extractelement <4 x float> %0, i64 1233 %2 = call i64 @llvm.llrint.i64.f32(float %vecext.1)234 %vecins.1 = insertelement <4 x i64> %vecins, i64 %2, i64 1235 %vecext.2 = extractelement <4 x float> %0, i64 2236 %3 = call i64 @llvm.llrint.i64.f32(float %vecext.2)237 %vecins.2 = insertelement <4 x i64> %vecins.1, i64 %3, i64 2238 %vecext.3 = extractelement <4 x float> %0, i64 3239 %4 = call i64 @llvm.llrint.i64.f32(float %vecext.3)240 %vecins.3 = insertelement <4 x i64> %vecins.2, i64 %4, i64 3241 ret <4 x i64> %vecins.3242}243 244define <8 x i64> @llrint_v8i64f32(ptr %a) {245; CHECK-LABEL: define <8 x i64> @llrint_v8i64f32(246; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {247; CHECK-NEXT: entry:248; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[A]], align 32249; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>250; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> [[TMP1]])251; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>252; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>253; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> [[TMP4]])254; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>255; CHECK-NEXT: [[VECINS_71:%.*]] = shufflevector <8 x i64> [[TMP3]], <8 x i64> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>256; CHECK-NEXT: ret <8 x i64> [[VECINS_71]]257;258entry:259 %0 = load <8 x float>, ptr %a260 %vecext = extractelement <8 x float> %0, i64 0261 %1 = call i64 @llvm.llrint.i64.f32(float %vecext)262 %vecins = insertelement <8 x i64> undef, i64 %1, i64 0263 %vecext.1 = extractelement <8 x float> %0, i64 1264 %2 = call i64 @llvm.llrint.i64.f32(float %vecext.1)265 %vecins.1 = insertelement <8 x i64> %vecins, i64 %2, i64 1266 %vecext.2 = extractelement <8 x float> %0, i64 2267 %3 = call i64 @llvm.llrint.i64.f32(float %vecext.2)268 %vecins.2 = insertelement <8 x i64> %vecins.1, i64 %3, i64 2269 %vecext.3 = extractelement <8 x float> %0, i64 3270 %4 = call i64 @llvm.llrint.i64.f32(float %vecext.3)271 %vecins.3 = insertelement <8 x i64> %vecins.2, i64 %4, i64 3272 %vecext.4 = extractelement <8 x float> %0, i64 4273 %5 = call i64 @llvm.llrint.i64.f32(float %vecext.4)274 %vecins.4 = insertelement <8 x i64> %vecins.3, i64 %5, i64 4275 %vecext.5 = extractelement <8 x float> %0, i64 5276 %6 = call i64 @llvm.llrint.i64.f32(float %vecext.5)277 %vecins.5 = insertelement <8 x i64> %vecins.4, i64 %6, i64 5278 %vecext.6 = extractelement <8 x float> %0, i64 6279 %7 = call i64 @llvm.llrint.i64.f32(float %vecext.6)280 %vecins.6 = insertelement <8 x i64> %vecins.5, i64 %7, i64 6281 %vecext.7 = extractelement <8 x float> %0, i64 7282 %8 = call i64 @llvm.llrint.i64.f32(float %vecext.7)283 %vecins.7 = insertelement <8 x i64> %vecins.6, i64 %8, i64 7284 ret <8 x i64> %vecins.7285}286 287declare float @llvm.rint.f32(float)288declare i32 @llvm.lrint.i32.f32(float)289declare i64 @llvm.lrint.i64.f32(float)290declare i64 @llvm.llrint.i64.f32(float)291