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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s3 4define fastcc void @rephase(ptr %phases_in, ptr %157, i64 %158) {5; CHECK-LABEL: define fastcc void @rephase(6; CHECK-SAME: ptr [[PHASES_IN:%.*]], ptr [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP1]]9; CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 810; CHECK-NEXT: [[IMAG_247:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 40811; CHECK-NEXT: [[IMAG_1_251:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 42412; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[IMAG_1_251]], align 813; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 014; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> zeroinitializer15; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>16; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison>, <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>17; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x double> [[TMP5]], [[TMP6]]18; CHECK-NEXT: store <4 x double> [[TMP7]], ptr [[IMAG_247]], align 819; CHECK-NEXT: store double [[TMP2]], ptr [[PHASES_IN]], align 820; CHECK-NEXT: ret void21;22entry:23 %ind.end11 = getelementptr i8, ptr %157, i64 %15824 %186 = load double, ptr %157, align 825 %imag.247 = getelementptr i8, ptr %ind.end11, i64 40826 %mul35.248 = fmul double %186, 0.000000e+0027 store double %mul35.248, ptr %imag.247, align 828 %arrayidx23.1.249 = getelementptr i8, ptr %ind.end11, i64 41629 %mul.1.250 = fmul double %186, 0.000000e+0030 store double %mul.1.250, ptr %arrayidx23.1.249, align 831 %imag.1.251 = getelementptr i8, ptr %ind.end11, i64 42432 %187 = load double, ptr %imag.1.251, align 833 %mul35.1.252 = fmul double %186, %18734 store double %mul35.1.252, ptr %imag.1.251, align 835 %arrayidx23.2.253 = getelementptr i8, ptr %ind.end11, i64 43236 %188 = load double, ptr %arrayidx23.2.253, align 837 %mul.2.254 = fmul double %186, %18838 store double %mul.2.254, ptr %arrayidx23.2.253, align 839 store double %186, ptr %phases_in, align 840 ret void41}42 43