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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s3 4define i32 @test() {5; CHECK-LABEL: define i32 @test(6; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr null, i64 16), align 89; CHECK-NEXT: [[SHR_1_I:%.*]] = lshr i64 0, 010; CHECK-NEXT: [[SHR_1_I_13:%.*]] = lshr i64 0, [[TMP0]]11; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[SHR_1_I_13]] to i812; CHECK-NEXT: [[STOREDV_1_I_13:%.*]] = and i8 0, [[TMP1]]13; CHECK-NEXT: [[SHR_1_I_14:%.*]] = lshr i64 0, [[TMP0]]14; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[SHR_1_I_14]] to i815; CHECK-NEXT: [[STOREDV_1_I_14:%.*]] = and i8 [[STOREDV_1_I_13]], [[TMP2]]16; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr (i8, ptr null, i64 32), align 817; CHECK-NEXT: [[SHR_2_I:%.*]] = lshr i64 0, [[TMP3]]18; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SHR_2_I]] to i819; CHECK-NEXT: [[STOREDV_2_I:%.*]] = and i8 [[STOREDV_1_I_14]], [[TMP4]]20; CHECK-NEXT: [[SHR_2_I_1:%.*]] = lshr i64 0, [[TMP3]]21; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[SHR_2_I_1]] to i822; CHECK-NEXT: [[STOREDV_2_I_1:%.*]] = and i8 [[STOREDV_2_I]], [[TMP5]]23; CHECK-NEXT: [[SHR_2_I_2:%.*]] = lshr i64 0, [[TMP3]]24; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[SHR_2_I_2]] to i825; CHECK-NEXT: [[STOREDV_2_I_2:%.*]] = and i8 [[STOREDV_2_I_1]], [[TMP6]]26; CHECK-NEXT: [[SHR_2_I_3:%.*]] = lshr i64 0, [[TMP3]]27; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[SHR_2_I_3]] to i828; CHECK-NEXT: [[STOREDV_2_I_3:%.*]] = and i8 [[STOREDV_2_I_2]], [[TMP7]]29; CHECK-NEXT: [[SHR_2_I_4:%.*]] = lshr i64 0, [[TMP3]]30; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[SHR_2_I_4]] to i831; CHECK-NEXT: [[STOREDV_2_I_4:%.*]] = and i8 [[STOREDV_2_I_3]], [[TMP8]]32; CHECK-NEXT: [[SHR_2_I_5:%.*]] = lshr i64 0, [[TMP3]]33; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[SHR_2_I_5]] to i834; CHECK-NEXT: [[STOREDV_2_I_5:%.*]] = and i8 [[STOREDV_2_I_4]], [[TMP9]]35; CHECK-NEXT: [[SHR_2_I_6:%.*]] = lshr i64 0, [[TMP3]]36; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[SHR_2_I_6]] to i837; CHECK-NEXT: [[STOREDV_2_I_6:%.*]] = and i8 [[STOREDV_2_I_5]], [[TMP10]]38; CHECK-NEXT: [[SHR_2_I_7:%.*]] = lshr i64 0, [[TMP3]]39; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[SHR_2_I_7]] to i840; CHECK-NEXT: [[STOREDV_2_I_7:%.*]] = and i8 [[STOREDV_2_I_6]], [[TMP11]]41; CHECK-NEXT: [[STOREDV_2_I_8:%.*]] = and i8 [[STOREDV_2_I_7]], 042; CHECK-NEXT: [[SHR_2_I_9:%.*]] = lshr i64 0, [[TMP3]]43; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[SHR_2_I_9]] to i844; CHECK-NEXT: [[STOREDV_2_I_9:%.*]] = and i8 [[STOREDV_2_I_8]], [[TMP12]]45; CHECK-NEXT: [[SHR_2_I_10:%.*]] = lshr i64 0, [[TMP3]]46; CHECK-NEXT: [[TMP13:%.*]] = trunc i64 [[SHR_2_I_10]] to i847; CHECK-NEXT: [[STOREDV_2_I_10:%.*]] = and i8 [[STOREDV_2_I_9]], [[TMP13]]48; CHECK-NEXT: [[SHR_2_I_11:%.*]] = lshr i64 0, [[TMP3]]49; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[SHR_2_I_11]] to i850; CHECK-NEXT: [[STOREDV_2_I_11:%.*]] = and i8 [[STOREDV_2_I_10]], [[TMP14]]51; CHECK-NEXT: [[SHR_2_I_12:%.*]] = lshr i64 0, [[TMP3]]52; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[SHR_2_I_12]] to i853; CHECK-NEXT: [[STOREDV_2_I_12:%.*]] = and i8 [[STOREDV_2_I_11]], [[TMP15]]54; CHECK-NEXT: [[SHR_2_I_13:%.*]] = lshr i64 0, [[TMP3]]55; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[SHR_2_I_13]] to i856; CHECK-NEXT: [[STOREDV_2_I_13:%.*]] = and i8 [[STOREDV_2_I_12]], [[TMP16]]57; CHECK-NEXT: [[STOREDV_2_I_14:%.*]] = and i8 [[STOREDV_2_I_13]], 058; CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr getelementptr (i8, ptr null, i64 48), align 859; CHECK-NEXT: [[SHR_3_I:%.*]] = lshr i64 0, [[TMP17]]60; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[SHR_3_I]] to i861; CHECK-NEXT: [[STOREDV_3_I:%.*]] = and i8 [[STOREDV_2_I_14]], [[TMP18]]62; CHECK-NEXT: [[SHR_3_I_1:%.*]] = lshr i64 0, [[TMP17]]63; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[SHR_3_I_1]] to i864; CHECK-NEXT: [[STOREDV_3_I_1:%.*]] = and i8 [[STOREDV_3_I]], [[TMP19]]65; CHECK-NEXT: [[STOREDV_3_I_2:%.*]] = and i8 [[STOREDV_3_I_1]], 066; CHECK-NEXT: [[SHR_3_I_3:%.*]] = lshr i64 0, [[TMP17]]67; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[SHR_3_I_3]] to i868; CHECK-NEXT: [[STOREDV_3_I_3:%.*]] = and i8 [[STOREDV_3_I_2]], [[TMP20]]69; CHECK-NEXT: [[SHR_3_I_4:%.*]] = lshr i64 0, [[TMP17]]70; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[SHR_3_I_4]] to i871; CHECK-NEXT: [[STOREDV_3_I_4:%.*]] = and i8 [[STOREDV_3_I_3]], [[TMP21]]72; CHECK-NEXT: [[SHR_3_I_5:%.*]] = lshr i64 0, [[TMP17]]73; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[SHR_3_I_5]] to i874; CHECK-NEXT: [[STOREDV_3_I_5:%.*]] = and i8 [[STOREDV_3_I_4]], [[TMP22]]75; CHECK-NEXT: [[STOREDV_3_I_6:%.*]] = and i8 [[STOREDV_3_I_5]], 076; CHECK-NEXT: [[SHR_3_I_7:%.*]] = lshr i64 0, [[TMP17]]77; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[SHR_3_I_7]] to i878; CHECK-NEXT: [[STOREDV_3_I_7:%.*]] = and i8 [[STOREDV_3_I_6]], [[TMP23]]79; CHECK-NEXT: [[SHR_3_I_8:%.*]] = lshr i64 0, [[TMP17]]80; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[SHR_3_I_8]] to i881; CHECK-NEXT: [[STOREDV_3_I_8:%.*]] = and i8 [[STOREDV_3_I_7]], [[TMP24]]82; CHECK-NEXT: [[SHR_3_I_9:%.*]] = lshr i64 0, [[TMP17]]83; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[SHR_3_I_9]] to i884; CHECK-NEXT: [[STOREDV_3_I_9:%.*]] = and i8 [[STOREDV_3_I_8]], [[TMP25]]85; CHECK-NEXT: [[SHR_3_I_10:%.*]] = lshr i64 0, [[TMP17]]86; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[SHR_3_I_10]] to i887; CHECK-NEXT: [[STOREDV_3_I_10:%.*]] = and i8 [[STOREDV_3_I_9]], [[TMP26]]88; CHECK-NEXT: [[SHR_3_I_11:%.*]] = lshr i64 0, [[TMP17]]89; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[SHR_3_I_11]] to i890; CHECK-NEXT: [[STOREDV_3_I_11:%.*]] = and i8 [[STOREDV_3_I_10]], [[TMP27]]91; CHECK-NEXT: [[STOREDV_3_I_12:%.*]] = and i8 [[STOREDV_3_I_11]], 092; CHECK-NEXT: [[SHR_3_I_13:%.*]] = lshr i64 0, [[TMP17]]93; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[SHR_3_I_13]] to i894; CHECK-NEXT: [[STOREDV_3_I_13:%.*]] = and i8 [[STOREDV_3_I_12]], [[TMP28]]95; CHECK-NEXT: [[SHR_3_I_14:%.*]] = lshr i64 0, [[TMP17]]96; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[SHR_3_I_14]] to i897; CHECK-NEXT: [[STOREDV_3_I_14:%.*]] = and i8 [[STOREDV_3_I_13]], [[TMP29]]98; CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr null, align 899; CHECK-NEXT: [[STOREDV_4_I:%.*]] = and i8 [[STOREDV_3_I_14]], 0100; CHECK-NEXT: [[SHR_4_I_1:%.*]] = lshr i64 0, [[TMP30]]101; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[SHR_4_I_1]] to i8102; CHECK-NEXT: [[STOREDV_4_I_1:%.*]] = and i8 [[STOREDV_4_I]], [[TMP31]]103; CHECK-NEXT: [[SHR_4_I_2:%.*]] = lshr i64 0, [[TMP30]]104; CHECK-NEXT: [[TMP32:%.*]] = trunc i64 [[SHR_4_I_2]] to i8105; CHECK-NEXT: [[STOREDV_4_I_2:%.*]] = and i8 [[STOREDV_4_I_1]], [[TMP32]]106; CHECK-NEXT: [[SHR_4_I_3:%.*]] = lshr i64 0, [[TMP30]]107; CHECK-NEXT: [[TMP33:%.*]] = trunc i64 [[SHR_4_I_3]] to i8108; CHECK-NEXT: [[STOREDV_4_I_3:%.*]] = and i8 [[STOREDV_4_I_2]], [[TMP33]]109; CHECK-NEXT: [[SHR_4_I_4:%.*]] = lshr i64 0, [[TMP30]]110; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[SHR_4_I_4]] to i8111; CHECK-NEXT: [[STOREDV_4_I_4:%.*]] = and i8 [[STOREDV_4_I_3]], [[TMP34]]112; CHECK-NEXT: [[STOREDV_4_I_5:%.*]] = and i8 [[STOREDV_4_I_4]], 0113; CHECK-NEXT: [[SHR_4_I_6:%.*]] = lshr i64 0, [[TMP30]]114; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[SHR_4_I_6]] to i8115; CHECK-NEXT: [[STOREDV_4_I_6:%.*]] = and i8 [[STOREDV_4_I_5]], [[TMP35]]116; CHECK-NEXT: [[SHR_4_I_7:%.*]] = lshr i64 0, [[TMP30]]117; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[SHR_4_I_7]] to i8118; CHECK-NEXT: [[STOREDV_4_I_7:%.*]] = and i8 [[STOREDV_4_I_6]], [[TMP36]]119; CHECK-NEXT: [[SHR_4_I_8:%.*]] = lshr i64 0, [[TMP30]]120; CHECK-NEXT: [[TMP37:%.*]] = trunc i64 [[SHR_4_I_8]] to i8121; CHECK-NEXT: [[STOREDV_4_I_8:%.*]] = and i8 [[STOREDV_4_I_7]], [[TMP37]]122; CHECK-NEXT: [[SHR_4_I_9:%.*]] = lshr i64 0, [[TMP30]]123; CHECK-NEXT: [[TMP38:%.*]] = trunc i64 [[SHR_4_I_9]] to i8124; CHECK-NEXT: [[STOREDV_4_I_9:%.*]] = and i8 [[STOREDV_4_I_8]], [[TMP38]]125; CHECK-NEXT: [[SHR_4_I_10:%.*]] = lshr i64 0, [[TMP30]]126; CHECK-NEXT: [[TMP39:%.*]] = trunc i64 [[SHR_4_I_10]] to i8127; CHECK-NEXT: [[STOREDV_4_I_10:%.*]] = and i8 [[STOREDV_4_I_9]], [[TMP39]]128; CHECK-NEXT: [[STOREDV_4_I_11:%.*]] = and i8 [[STOREDV_4_I_10]], 0129; CHECK-NEXT: [[SHR_4_I_12:%.*]] = lshr i64 0, [[TMP30]]130; CHECK-NEXT: [[TMP40:%.*]] = trunc i64 [[SHR_4_I_12]] to i8131; CHECK-NEXT: [[STOREDV_4_I_12:%.*]] = and i8 [[STOREDV_4_I_11]], [[TMP40]]132; CHECK-NEXT: [[SHR_4_I_13:%.*]] = lshr i64 0, [[TMP30]]133; CHECK-NEXT: [[TMP41:%.*]] = trunc i64 [[SHR_4_I_13]] to i8134; CHECK-NEXT: [[STOREDV_4_I_13:%.*]] = and i8 [[STOREDV_4_I_12]], [[TMP41]]135; CHECK-NEXT: [[SHR_4_I_14:%.*]] = lshr i64 0, [[TMP30]]136; CHECK-NEXT: [[TMP42:%.*]] = trunc i64 [[SHR_4_I_14]] to i8137; CHECK-NEXT: [[STOREDV_4_I_14:%.*]] = and i8 [[STOREDV_4_I_13]], [[TMP42]]138; CHECK-NEXT: [[TMP43:%.*]] = load i64, ptr getelementptr (i8, ptr null, i64 80), align 8139; CHECK-NEXT: [[SHR_5_I:%.*]] = lshr i64 0, [[TMP43]]140; CHECK-NEXT: [[TMP44:%.*]] = trunc i64 [[SHR_5_I]] to i8141; CHECK-NEXT: [[STOREDV_5_I:%.*]] = and i8 [[STOREDV_4_I_14]], [[TMP44]]142; CHECK-NEXT: [[SHR_5_I_1:%.*]] = lshr i64 0, [[TMP43]]143; CHECK-NEXT: [[TMP45:%.*]] = trunc i64 [[SHR_5_I_1]] to i8144; CHECK-NEXT: [[STOREDV_5_I_1:%.*]] = and i8 [[STOREDV_5_I]], [[TMP45]]145; CHECK-NEXT: [[SHR_5_I_2:%.*]] = lshr i64 0, [[TMP43]]146; CHECK-NEXT: [[TMP46:%.*]] = trunc i64 [[SHR_5_I_2]] to i8147; CHECK-NEXT: [[STOREDV_5_I_2:%.*]] = and i8 [[STOREDV_5_I_1]], [[TMP46]]148; CHECK-NEXT: [[STOREDV_5_I_3:%.*]] = and i8 [[STOREDV_5_I_2]], 0149; CHECK-NEXT: [[SHR_5_I_4:%.*]] = lshr i64 0, [[TMP43]]150; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[SHR_5_I_4]] to i8151; CHECK-NEXT: [[STOREDV_5_I_4:%.*]] = and i8 [[STOREDV_5_I_3]], [[TMP47]]152; CHECK-NEXT: [[SHR_5_I_5:%.*]] = lshr i64 0, [[TMP43]]153; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[SHR_5_I_5]] to i8154; CHECK-NEXT: [[STOREDV_5_I_5:%.*]] = and i8 [[STOREDV_5_I_4]], [[TMP48]]155; CHECK-NEXT: [[SHR_5_I_6:%.*]] = lshr i64 0, [[TMP43]]156; CHECK-NEXT: [[TMP49:%.*]] = trunc i64 [[SHR_5_I_6]] to i8157; CHECK-NEXT: [[STOREDV_5_I_6:%.*]] = and i8 [[STOREDV_5_I_5]], [[TMP49]]158; CHECK-NEXT: [[SHR_5_I_7:%.*]] = lshr i64 0, [[TMP43]]159; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[SHR_5_I_7]] to i8160; CHECK-NEXT: [[STOREDV_5_I_7:%.*]] = and i8 [[STOREDV_5_I_6]], [[TMP50]]161; CHECK-NEXT: [[SHR_5_I_8:%.*]] = lshr i64 0, [[TMP43]]162; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[SHR_5_I_8]] to i8163; CHECK-NEXT: [[STOREDV_5_I_8:%.*]] = and i8 [[STOREDV_5_I_7]], [[TMP51]]164; CHECK-NEXT: [[STOREDV_5_I_9:%.*]] = and i8 [[STOREDV_5_I_8]], 0165; CHECK-NEXT: [[SHR_5_I_10:%.*]] = lshr i64 0, [[TMP43]]166; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[SHR_5_I_10]] to i8167; CHECK-NEXT: [[STOREDV_5_I_10:%.*]] = and i8 [[STOREDV_5_I_9]], [[TMP52]]168; CHECK-NEXT: [[SHR_5_I_11:%.*]] = lshr i64 0, [[TMP43]]169; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[SHR_5_I_11]] to i8170; CHECK-NEXT: [[STOREDV_5_I_11:%.*]] = and i8 [[STOREDV_5_I_10]], [[TMP53]]171; CHECK-NEXT: [[SHR_5_I_12:%.*]] = lshr i64 0, [[TMP43]]172; CHECK-NEXT: [[TMP54:%.*]] = trunc i64 [[SHR_5_I_12]] to i8173; CHECK-NEXT: [[STOREDV_5_I_12:%.*]] = and i8 [[STOREDV_5_I_11]], [[TMP54]]174; CHECK-NEXT: [[SHR_5_I_13:%.*]] = lshr i64 0, [[TMP43]]175; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[SHR_5_I_13]] to i8176; CHECK-NEXT: [[STOREDV_5_I_13:%.*]] = and i8 [[STOREDV_5_I_12]], [[TMP55]]177; CHECK-NEXT: [[SHR_5_I_14:%.*]] = lshr i64 0, [[TMP43]]178; CHECK-NEXT: [[TMP56:%.*]] = trunc i64 [[SHR_5_I_14]] to i8179; CHECK-NEXT: [[STOREDV_5_I_14:%.*]] = and i8 [[STOREDV_5_I_13]], [[TMP56]]180; CHECK-NEXT: [[TMP57:%.*]] = load i64, ptr null, align 8181; CHECK-NEXT: [[SHR_6_I:%.*]] = lshr i64 0, [[TMP57]]182; CHECK-NEXT: [[TMP58:%.*]] = trunc i64 [[SHR_6_I]] to i8183; CHECK-NEXT: [[STOREDV_6_I:%.*]] = and i8 [[STOREDV_5_I_14]], [[TMP58]]184; CHECK-NEXT: [[SHR_6_I_1:%.*]] = lshr i64 0, [[TMP57]]185; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[SHR_6_I_1]] to i8186; CHECK-NEXT: [[STOREDV_6_I_1:%.*]] = and i8 [[STOREDV_6_I]], [[TMP59]]187; CHECK-NEXT: [[SHR_6_I_2:%.*]] = lshr i64 0, [[TMP57]]188; CHECK-NEXT: [[TMP60:%.*]] = trunc i64 [[SHR_6_I_2]] to i8189; CHECK-NEXT: [[STOREDV_6_I_2:%.*]] = and i8 [[STOREDV_6_I_1]], [[TMP60]]190; CHECK-NEXT: [[STOREDV_6_I_3:%.*]] = and i8 [[STOREDV_6_I_2]], 0191; CHECK-NEXT: [[SHR_6_I_4:%.*]] = lshr i64 0, [[TMP57]]192; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[SHR_6_I_4]] to i8193; CHECK-NEXT: [[STOREDV_6_I_4:%.*]] = and i8 [[STOREDV_6_I_3]], [[TMP61]]194; CHECK-NEXT: [[SHR_6_I_5:%.*]] = lshr i64 0, [[TMP57]]195; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[SHR_6_I_5]] to i8196; CHECK-NEXT: [[STOREDV_6_I_5:%.*]] = and i8 [[STOREDV_6_I_4]], [[TMP62]]197; CHECK-NEXT: [[SHR_6_I_6:%.*]] = lshr i64 0, [[TMP57]]198; CHECK-NEXT: [[TMP63:%.*]] = trunc i64 [[SHR_6_I_6]] to i8199; CHECK-NEXT: [[STOREDV_6_I_6:%.*]] = and i8 [[STOREDV_6_I_5]], [[TMP63]]200; CHECK-NEXT: [[SHR_6_I_7:%.*]] = lshr i64 0, [[TMP57]]201; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[SHR_6_I_7]] to i8202; CHECK-NEXT: [[STOREDV_6_I_7:%.*]] = and i8 [[STOREDV_6_I_6]], [[TMP64]]203; CHECK-NEXT: [[STOREDV_6_I_8:%.*]] = and i8 [[STOREDV_6_I_7]], 0204; CHECK-NEXT: [[SHR_6_I_9:%.*]] = lshr i64 0, [[TMP57]]205; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[SHR_6_I_9]] to i8206; CHECK-NEXT: [[STOREDV_6_I_9:%.*]] = and i8 [[STOREDV_6_I_8]], [[TMP65]]207; CHECK-NEXT: [[SHR_6_I_10:%.*]] = lshr i64 0, [[TMP57]]208; CHECK-NEXT: [[TMP66:%.*]] = trunc i64 [[SHR_6_I_10]] to i8209; CHECK-NEXT: [[STOREDV_6_I_10:%.*]] = and i8 [[STOREDV_6_I_9]], [[TMP66]]210; CHECK-NEXT: [[SHR_6_I_11:%.*]] = lshr i64 0, [[TMP57]]211; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[SHR_6_I_11]] to i8212; CHECK-NEXT: [[STOREDV_6_I_11:%.*]] = and i8 [[STOREDV_6_I_10]], [[TMP67]]213; CHECK-NEXT: [[SHR_6_I_12:%.*]] = lshr i64 0, [[TMP57]]214; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[SHR_6_I_12]] to i8215; CHECK-NEXT: [[STOREDV_6_I_12:%.*]] = and i8 [[STOREDV_6_I_11]], [[TMP68]]216; CHECK-NEXT: [[STOREDV_6_I_13:%.*]] = and i8 [[STOREDV_6_I_12]], 0217; CHECK-NEXT: [[SHR_6_I_14:%.*]] = lshr i64 0, 0218; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[SHR_6_I_14]] to i8219; CHECK-NEXT: [[STOREDV_6_I_14:%.*]] = and i8 [[STOREDV_6_I_13]], [[TMP69]]220; CHECK-NEXT: store i8 [[STOREDV_6_I_14]], ptr null, align 1221; CHECK-NEXT: ret i32 0222;223entry:224 %0 = load i64, ptr getelementptr (i8, ptr null, i64 16), align 8225 %shr.1.i = lshr i64 0, 0226 %shr.1.i.13 = lshr i64 0, %0227 %1 = trunc i64 %shr.1.i.13 to i8228 %storedv.1.i.13 = and i8 0, %1229 %shr.1.i.14 = lshr i64 0, %0230 %2 = trunc i64 %shr.1.i.14 to i8231 %storedv.1.i.14 = and i8 %storedv.1.i.13, %2232 %3 = load i64, ptr getelementptr (i8, ptr null, i64 32), align 8233 %shr.2.i = lshr i64 0, %3234 %4 = trunc i64 %shr.2.i to i8235 %storedv.2.i = and i8 %storedv.1.i.14, %4236 %shr.2.i.1 = lshr i64 0, %3237 %5 = trunc i64 %shr.2.i.1 to i8238 %storedv.2.i.1 = and i8 %storedv.2.i, %5239 %shr.2.i.2 = lshr i64 0, %3240 %6 = trunc i64 %shr.2.i.2 to i8241 %storedv.2.i.2 = and i8 %storedv.2.i.1, %6242 %shr.2.i.3 = lshr i64 0, %3243 %7 = trunc i64 %shr.2.i.3 to i8244 %storedv.2.i.3 = and i8 %storedv.2.i.2, %7245 %shr.2.i.4 = lshr i64 0, %3246 %8 = trunc i64 %shr.2.i.4 to i8247 %storedv.2.i.4 = and i8 %storedv.2.i.3, %8248 %shr.2.i.5 = lshr i64 0, %3249 %9 = trunc i64 %shr.2.i.5 to i8250 %storedv.2.i.5 = and i8 %storedv.2.i.4, %9251 %shr.2.i.6 = lshr i64 0, %3252 %10 = trunc i64 %shr.2.i.6 to i8253 %storedv.2.i.6 = and i8 %storedv.2.i.5, %10254 %shr.2.i.7 = lshr i64 0, %3255 %11 = trunc i64 %shr.2.i.7 to i8256 %storedv.2.i.7 = and i8 %storedv.2.i.6, %11257 %storedv.2.i.8 = and i8 %storedv.2.i.7, 0258 %shr.2.i.9 = lshr i64 0, %3259 %12 = trunc i64 %shr.2.i.9 to i8260 %storedv.2.i.9 = and i8 %storedv.2.i.8, %12261 %shr.2.i.10 = lshr i64 0, %3262 %13 = trunc i64 %shr.2.i.10 to i8263 %storedv.2.i.10 = and i8 %storedv.2.i.9, %13264 %shr.2.i.11 = lshr i64 0, %3265 %14 = trunc i64 %shr.2.i.11 to i8266 %storedv.2.i.11 = and i8 %storedv.2.i.10, %14267 %shr.2.i.12 = lshr i64 0, %3268 %15 = trunc i64 %shr.2.i.12 to i8269 %storedv.2.i.12 = and i8 %storedv.2.i.11, %15270 %shr.2.i.13 = lshr i64 0, %3271 %16 = trunc i64 %shr.2.i.13 to i8272 %storedv.2.i.13 = and i8 %storedv.2.i.12, %16273 %storedv.2.i.14 = and i8 %storedv.2.i.13, 0274 %17 = load i64, ptr getelementptr (i8, ptr null, i64 48), align 8275 %shr.3.i = lshr i64 0, %17276 %18 = trunc i64 %shr.3.i to i8277 %storedv.3.i = and i8 %storedv.2.i.14, %18278 %shr.3.i.1 = lshr i64 0, %17279 %19 = trunc i64 %shr.3.i.1 to i8280 %storedv.3.i.1 = and i8 %storedv.3.i, %19281 %storedv.3.i.2 = and i8 %storedv.3.i.1, 0282 %shr.3.i.3 = lshr i64 0, %17283 %20 = trunc i64 %shr.3.i.3 to i8284 %storedv.3.i.3 = and i8 %storedv.3.i.2, %20285 %shr.3.i.4 = lshr i64 0, %17286 %21 = trunc i64 %shr.3.i.4 to i8287 %storedv.3.i.4 = and i8 %storedv.3.i.3, %21288 %shr.3.i.5 = lshr i64 0, %17289 %22 = trunc i64 %shr.3.i.5 to i8290 %storedv.3.i.5 = and i8 %storedv.3.i.4, %22291 %storedv.3.i.6 = and i8 %storedv.3.i.5, 0292 %shr.3.i.7 = lshr i64 0, %17293 %23 = trunc i64 %shr.3.i.7 to i8294 %storedv.3.i.7 = and i8 %storedv.3.i.6, %23295 %shr.3.i.8 = lshr i64 0, %17296 %24 = trunc i64 %shr.3.i.8 to i8297 %storedv.3.i.8 = and i8 %storedv.3.i.7, %24298 %shr.3.i.9 = lshr i64 0, %17299 %25 = trunc i64 %shr.3.i.9 to i8300 %storedv.3.i.9 = and i8 %storedv.3.i.8, %25301 %shr.3.i.10 = lshr i64 0, %17302 %26 = trunc i64 %shr.3.i.10 to i8303 %storedv.3.i.10 = and i8 %storedv.3.i.9, %26304 %shr.3.i.11 = lshr i64 0, %17305 %27 = trunc i64 %shr.3.i.11 to i8306 %storedv.3.i.11 = and i8 %storedv.3.i.10, %27307 %storedv.3.i.12 = and i8 %storedv.3.i.11, 0308 %shr.3.i.13 = lshr i64 0, %17309 %28 = trunc i64 %shr.3.i.13 to i8310 %storedv.3.i.13 = and i8 %storedv.3.i.12, %28311 %shr.3.i.14 = lshr i64 0, %17312 %29 = trunc i64 %shr.3.i.14 to i8313 %storedv.3.i.14 = and i8 %storedv.3.i.13, %29314 %30 = load i64, ptr null, align 8315 %storedv.4.i = and i8 %storedv.3.i.14, 0316 %shr.4.i.1 = lshr i64 0, %30317 %31 = trunc i64 %shr.4.i.1 to i8318 %storedv.4.i.1 = and i8 %storedv.4.i, %31319 %shr.4.i.2 = lshr i64 0, %30320 %32 = trunc i64 %shr.4.i.2 to i8321 %storedv.4.i.2 = and i8 %storedv.4.i.1, %32322 %shr.4.i.3 = lshr i64 0, %30323 %33 = trunc i64 %shr.4.i.3 to i8324 %storedv.4.i.3 = and i8 %storedv.4.i.2, %33325 %shr.4.i.4 = lshr i64 0, %30326 %34 = trunc i64 %shr.4.i.4 to i8327 %storedv.4.i.4 = and i8 %storedv.4.i.3, %34328 %storedv.4.i.5 = and i8 %storedv.4.i.4, 0329 %shr.4.i.6 = lshr i64 0, %30330 %35 = trunc i64 %shr.4.i.6 to i8331 %storedv.4.i.6 = and i8 %storedv.4.i.5, %35332 %shr.4.i.7 = lshr i64 0, %30333 %36 = trunc i64 %shr.4.i.7 to i8334 %storedv.4.i.7 = and i8 %storedv.4.i.6, %36335 %shr.4.i.8 = lshr i64 0, %30336 %37 = trunc i64 %shr.4.i.8 to i8337 %storedv.4.i.8 = and i8 %storedv.4.i.7, %37338 %shr.4.i.9 = lshr i64 0, %30339 %38 = trunc i64 %shr.4.i.9 to i8340 %storedv.4.i.9 = and i8 %storedv.4.i.8, %38341 %shr.4.i.10 = lshr i64 0, %30342 %39 = trunc i64 %shr.4.i.10 to i8343 %storedv.4.i.10 = and i8 %storedv.4.i.9, %39344 %storedv.4.i.11 = and i8 %storedv.4.i.10, 0345 %shr.4.i.12 = lshr i64 0, %30346 %40 = trunc i64 %shr.4.i.12 to i8347 %storedv.4.i.12 = and i8 %storedv.4.i.11, %40348 %shr.4.i.13 = lshr i64 0, %30349 %41 = trunc i64 %shr.4.i.13 to i8350 %storedv.4.i.13 = and i8 %storedv.4.i.12, %41351 %shr.4.i.14 = lshr i64 0, %30352 %42 = trunc i64 %shr.4.i.14 to i8353 %storedv.4.i.14 = and i8 %storedv.4.i.13, %42354 %43 = load i64, ptr getelementptr (i8, ptr null, i64 80), align 8355 %shr.5.i = lshr i64 0, %43356 %44 = trunc i64 %shr.5.i to i8357 %storedv.5.i = and i8 %storedv.4.i.14, %44358 %shr.5.i.1 = lshr i64 0, %43359 %45 = trunc i64 %shr.5.i.1 to i8360 %storedv.5.i.1 = and i8 %storedv.5.i, %45361 %shr.5.i.2 = lshr i64 0, %43362 %46 = trunc i64 %shr.5.i.2 to i8363 %storedv.5.i.2 = and i8 %storedv.5.i.1, %46364 %storedv.5.i.3 = and i8 %storedv.5.i.2, 0365 %shr.5.i.4 = lshr i64 0, %43366 %47 = trunc i64 %shr.5.i.4 to i8367 %storedv.5.i.4 = and i8 %storedv.5.i.3, %47368 %shr.5.i.5 = lshr i64 0, %43369 %48 = trunc i64 %shr.5.i.5 to i8370 %storedv.5.i.5 = and i8 %storedv.5.i.4, %48371 %shr.5.i.6 = lshr i64 0, %43372 %49 = trunc i64 %shr.5.i.6 to i8373 %storedv.5.i.6 = and i8 %storedv.5.i.5, %49374 %shr.5.i.7 = lshr i64 0, %43375 %50 = trunc i64 %shr.5.i.7 to i8376 %storedv.5.i.7 = and i8 %storedv.5.i.6, %50377 %shr.5.i.8 = lshr i64 0, %43378 %51 = trunc i64 %shr.5.i.8 to i8379 %storedv.5.i.8 = and i8 %storedv.5.i.7, %51380 %storedv.5.i.9 = and i8 %storedv.5.i.8, 0381 %shr.5.i.10 = lshr i64 0, %43382 %52 = trunc i64 %shr.5.i.10 to i8383 %storedv.5.i.10 = and i8 %storedv.5.i.9, %52384 %shr.5.i.11 = lshr i64 0, %43385 %53 = trunc i64 %shr.5.i.11 to i8386 %storedv.5.i.11 = and i8 %storedv.5.i.10, %53387 %shr.5.i.12 = lshr i64 0, %43388 %54 = trunc i64 %shr.5.i.12 to i8389 %storedv.5.i.12 = and i8 %storedv.5.i.11, %54390 %shr.5.i.13 = lshr i64 0, %43391 %55 = trunc i64 %shr.5.i.13 to i8392 %storedv.5.i.13 = and i8 %storedv.5.i.12, %55393 %shr.5.i.14 = lshr i64 0, %43394 %56 = trunc i64 %shr.5.i.14 to i8395 %storedv.5.i.14 = and i8 %storedv.5.i.13, %56396 %57 = load i64, ptr null, align 8397 %shr.6.i = lshr i64 0, %57398 %58 = trunc i64 %shr.6.i to i8399 %storedv.6.i = and i8 %storedv.5.i.14, %58400 %shr.6.i.1 = lshr i64 0, %57401 %59 = trunc i64 %shr.6.i.1 to i8402 %storedv.6.i.1 = and i8 %storedv.6.i, %59403 %shr.6.i.2 = lshr i64 0, %57404 %60 = trunc i64 %shr.6.i.2 to i8405 %storedv.6.i.2 = and i8 %storedv.6.i.1, %60406 %storedv.6.i.3 = and i8 %storedv.6.i.2, 0407 %shr.6.i.4 = lshr i64 0, %57408 %61 = trunc i64 %shr.6.i.4 to i8409 %storedv.6.i.4 = and i8 %storedv.6.i.3, %61410 %shr.6.i.5 = lshr i64 0, %57411 %62 = trunc i64 %shr.6.i.5 to i8412 %storedv.6.i.5 = and i8 %storedv.6.i.4, %62413 %shr.6.i.6 = lshr i64 0, %57414 %63 = trunc i64 %shr.6.i.6 to i8415 %storedv.6.i.6 = and i8 %storedv.6.i.5, %63416 %shr.6.i.7 = lshr i64 0, %57417 %64 = trunc i64 %shr.6.i.7 to i8418 %storedv.6.i.7 = and i8 %storedv.6.i.6, %64419 %storedv.6.i.8 = and i8 %storedv.6.i.7, 0420 %shr.6.i.9 = lshr i64 0, %57421 %65 = trunc i64 %shr.6.i.9 to i8422 %storedv.6.i.9 = and i8 %storedv.6.i.8, %65423 %shr.6.i.10 = lshr i64 0, %57424 %66 = trunc i64 %shr.6.i.10 to i8425 %storedv.6.i.10 = and i8 %storedv.6.i.9, %66426 %shr.6.i.11 = lshr i64 0, %57427 %67 = trunc i64 %shr.6.i.11 to i8428 %storedv.6.i.11 = and i8 %storedv.6.i.10, %67429 %shr.6.i.12 = lshr i64 0, %57430 %68 = trunc i64 %shr.6.i.12 to i8431 %storedv.6.i.12 = and i8 %storedv.6.i.11, %68432 %storedv.6.i.13 = and i8 %storedv.6.i.12, 0433 %shr.6.i.14 = lshr i64 0, 0434 %69 = trunc i64 %shr.6.i.14 to i8435 %storedv.6.i.14 = and i8 %storedv.6.i.13, %69436 store i8 %storedv.6.i.14, ptr null, align 1437 ret i32 0438}439