58 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s3 4target triple = "riscv64-unknown-linux-gnu"5 6define void @partial_vec_invalid_cost() #0 {7; CHECK-LABEL: define void @partial_vec_invalid_cost(8; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: entry:10; CHECK-NEXT: [[LSHR_1:%.*]] = lshr i96 0, 011; CHECK-NEXT: [[LSHR_2:%.*]] = lshr i96 0, 012; CHECK-NEXT: [[TRUNC_I96_1:%.*]] = trunc i96 [[LSHR_1]] to i3213; CHECK-NEXT: [[TRUNC_I96_2:%.*]] = trunc i96 [[LSHR_2]] to i3214; CHECK-NEXT: [[TRUNC_I96_3:%.*]] = trunc i96 0 to i3215; CHECK-NEXT: [[TRUNC_I96_4:%.*]] = trunc i96 0 to i3216; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> zeroinitializer)17; CHECK-NEXT: [[OP_RDX:%.*]] = or i32 [[TMP1]], [[TRUNC_I96_1]]18; CHECK-NEXT: [[OP_RDX1:%.*]] = or i32 [[TRUNC_I96_2]], [[TRUNC_I96_3]]19; CHECK-NEXT: [[OP_RDX2:%.*]] = or i32 [[OP_RDX]], [[OP_RDX1]]20; CHECK-NEXT: [[OP_RDX3:%.*]] = or i32 [[OP_RDX2]], [[TRUNC_I96_4]]21; CHECK-NEXT: [[STORE_THIS:%.*]] = zext i32 [[OP_RDX3]] to i9622; CHECK-NEXT: store i96 [[STORE_THIS]], ptr null, align 1623; CHECK-NEXT: ret void24;25entry:26 27 %lshr.1 = lshr i96 0, 0 ; These ops28 %lshr.2 = lshr i96 0, 0 ; return an29 %add.0 = add i96 0, 0 ; invalid30 %add.1 = add i96 0, 0 ; vector cost.31 32 %trunc.i96.1 = trunc i96 %lshr.1 to i32 ; These ops33 %trunc.i96.2 = trunc i96 %lshr.2 to i32 ; return an34 %trunc.i96.3 = trunc i96 %add.0 to i32 ; invalid35 %trunc.i96.4 = trunc i96 %add.1 to i32 ; vector cost.36 37 %or.0 = or i32 %trunc.i96.1, %trunc.i96.238 %or.1 = or i32 %or.0, %trunc.i96.339 %or.2 = or i32 %or.1, %trunc.i96.440 41 %zext.0 = zext i1 0 to i32 ; These42 %zext.1 = zext i1 0 to i32 ; ops43 %zext.2 = zext i1 0 to i32 ; are44 %zext.3 = zext i1 0 to i32 ; vectorized45 46 %or.3 = or i32 %or.2, %zext.0 ; users47 %or.4 = or i32 %or.3, %zext.1 ; of48 %or.5 = or i32 %or.4, %zext.2 ; vectorized49 %or.6 = or i32 %or.5, %zext.3 ; ops50 51 %store.this = zext i32 %or.6 to i9652 53 store i96 %store.this, ptr null, align 1654 ret void55}56 57attributes #0 = { "target-features"="+v" }58