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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S -mtriple=riscv64-unknown-linux-gnu -mattr="+v" --passes=slp-vectorizer < %s | FileCheck %s3 4define i32 @test(ptr %0, ptr %1) {5; CHECK-LABEL: define i32 @test(6; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: entry:8; CHECK-NEXT: [[LOAD_5:%.*]] = load i32, ptr [[TMP1]], align 49; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> splat (i8 1))10; CHECK-NEXT: [[TMP3:%.*]] = sext i8 [[TMP2]] to i3211; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 [[TMP3]], [[LOAD_5]]12; CHECK-NEXT: ret i32 [[OP_RDX]]13;14entry:15 %zext.0 = zext i8 1 to i3216 %zext.1 = zext i8 1 to i3217 %zext.2 = zext i8 1 to i3218 %zext.3 = zext i8 1 to i3219 %select.zext.0 = select i1 false, i32 -1, i32 %zext.020 %select.zext.1 = select i1 false, i32 0, i32 %zext.121 %select.zext.2 = select i1 false, i32 0, i32 %zext.222 %select.zext.3 = select i1 false, i32 0, i32 %zext.323 24 %load.5 = load i32, ptr %1, align 425 26 %and.0 = and i32 %load.5, %select.zext.027 %and.1 = and i32 %and.0, %select.zext.128 %and.2 = and i32 %and.1, %select.zext.229 %and.3 = and i32 %and.2, %select.zext.330 31 ret i32 %and.332}33 34