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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s3 4define i32 @test(ptr %f, i16 %0) {5; CHECK-LABEL: define i32 @test(6; CHECK-SAME: ptr [[F:%.*]], i16 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: entry:8; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[F]], align 29; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP0]], i32 010; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP1]], i32 011; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>12; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i32>13; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <4 x i32> [[TMP6]], [[TMP7]]14; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP4]])15; CHECK-NEXT: [[ZEXT_4:%.*]] = zext i1 [[TMP5]] to i3216; CHECK-NEXT: ret i32 [[ZEXT_4]]17;18entry:19 %1 = load i16, ptr %f, align 220 21 %zext.0 = zext i16 %1 to i3222 %sext.0 = sext i16 %0 to i3223 24 %zext.1 = zext i16 0 to i3225 %sext.1 = sext i16 0 to i3226 %zext.2 = zext i16 0 to i3227 %sext.2 = sext i16 0 to i3228 %zext.3 = zext i16 0 to i3229 %sext.3 = sext i16 0 to i3230 31 %cmp.0 = icmp ule i32 %zext.0, %sext.032 %cmp.1 = icmp ule i32 %zext.1, %sext.133 %cmp.2 = icmp ule i32 %zext.2, %sext.234 %cmp.3 = icmp ule i32 %zext.3, %sext.335 36 %and.0 = and i1 %cmp.0, %cmp.137 %and.1 = and i1 %and.0, %cmp.238 %and.2 = and i1 %and.1, %cmp.339 40 %zext.4 = zext i1 %and.2 to i3241 42 ret i32 %zext.443}44