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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S --passes=slp-vectorizer -mtriple=systemz -mcpu=z15 %s | FileCheck %s3 4define void @test(ptr %a, i8 %0, i16 %b.promoted.i) {5; CHECK-LABEL: define void @test(6; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 08; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer9; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i1610; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 011; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer12; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]]13; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]])14; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP9]] to i6415; CHECK-NEXT: [[OP_RDX:%.*]] = and i64 [[TMP11]], 116; CHECK-NEXT: store i64 [[OP_RDX]], ptr [[A]], align 817; CHECK-NEXT: ret void18;19 %2 = zext i8 %0 to i12820 %3 = zext i16 %b.promoted.i to i12821 %4 = or i128 %3, %222 %5 = trunc i128 %4 to i6423 %6 = and i64 %5, 124 %7 = zext i16 %b.promoted.i to i12825 %8 = or i128 %7, %226 %9 = trunc i128 %8 to i6427 %10 = and i64 %6, %928 %11 = zext i16 %b.promoted.i to i12829 %12 = or i128 %11, %230 %13 = trunc i128 %12 to i6431 %14 = and i64 %10, %1332 %15 = zext i16 %b.promoted.i to i12833 %16 = or i128 %15, %234 %17 = trunc i128 %16 to i6435 %18 = and i64 %14, %1736 store i64 %18, ptr %a, align 837 ret void38}39 40