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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s3 4; Regression test for a bug in the SLP vectorizer that was causing5; these rotates to be incorrectly combined into a vector rotate.6 7target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"8target triple = "wasm32-unknown-unknown"9 10define void @foo(<2 x i64> %x, <4 x i32> %y, ptr %out) #0 {11; CHECK-LABEL: @foo(12; CHECK-NEXT: [[A:%.*]] = extractelement <2 x i64> [[X:%.*]], i32 013; CHECK-NEXT: [[B:%.*]] = extractelement <4 x i32> [[Y:%.*]], i32 214; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[B]] to i6415; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[A]], i64 [[A]], i64 [[CONV6]])16; CHECK-NEXT: store i64 [[C]], ptr [[OUT:%.*]], align 817; CHECK-NEXT: [[D:%.*]] = extractelement <2 x i64> [[X]], i32 118; CHECK-NEXT: [[E:%.*]] = extractelement <4 x i32> [[Y]], i32 319; CHECK-NEXT: [[CONV17:%.*]] = zext i32 [[E]] to i6420; CHECK-NEXT: [[F:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[D]], i64 [[D]], i64 [[CONV17]])21; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[OUT]], i32 122; CHECK-NEXT: store i64 [[F]], ptr [[ARRAYIDX2]], align 823; CHECK-NEXT: ret void24;25 %a = extractelement <2 x i64> %x, i32 026 %b = extractelement <4 x i32> %y, i32 227 %conv6 = zext i32 %b to i6428 %c = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %conv6)29 store i64 %c, ptr %out30 %d = extractelement <2 x i64> %x, i32 131 %e = extractelement <4 x i32> %y, i32 332 %conv17 = zext i32 %e to i6433 %f = tail call i64 @llvm.fshl.i64(i64 %d, i64 %d, i64 %conv17)34 %arrayidx2 = getelementptr inbounds i64, ptr %out, i32 135 store i64 %f, ptr %arrayidx236 ret void37}38 39declare i64 @llvm.fshl.i64(i64, i64, i64)40 41attributes #0 = {"target-cpu"="generic" "target-features"="+simd128"}42