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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s3 4define i16 @test(i16 %call37) {5; CHECK-LABEL: @test(6; CHECK-NEXT:  entry:7; CHECK-NEXT:    [[CALL:%.*]] = load i16, ptr undef, align 28; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 poison, i16 poison, i16 0, i16 poison, i16 0>, i16 [[CALL37:%.*]], i32 39; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i32 010; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 3, i32 7>11; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <8 x i16> [[SHUFFLE]], zeroinitializer12; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt <8 x i16> [[SHUFFLE]], zeroinitializer13; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 5, i32 6, i32 7>14; CHECK-NEXT:    [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i815; CHECK-NEXT:    [[TMP7:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP8]])16; CHECK-NEXT:    [[TMP6:%.*]] = zext i8 [[TMP7]] to i1617; CHECK-NEXT:    [[OP_RDX:%.*]] = add i16 [[TMP6]], 018; CHECK-NEXT:    ret i16 [[OP_RDX]]19;20entry:21  %call = load i16, ptr undef, align 222  %0 = icmp slt i16 %call, 023  %cond = zext i1 %0 to i1624  %1 = add i16 %cond, 025  %2 = icmp slt i16 0, 026  %cond32 = zext i1 %2 to i1627  %3 = add i16 %1, %cond3228  %.not = icmp sgt i16 0, %call3729  %cond55 = zext i1 %.not to i1630  %4 = icmp sgt i16 %call37, 031  %cond76 = zext i1 %4 to i1632  %5 = icmp slt i16 0, 033  %cond97 = zext i1 %5 to i1634  %.not206 = icmp sgt i16 0, %call3735  %cond120 = zext i1 %.not206 to i1636  %6 = icmp sgt i16 0, 037  %cond141 = zext i1 %6 to i1638  %7 = icmp slt i16 0, 039  %cond162 = zext i1 %7 to i1640  %8 = add i16 %3, %cond9741  %9 = add i16 %8, %cond5542  %10 = add i16 %9, %cond7643  %11 = add i16 %10, %cond16244  %12 = add i16 %11, %cond12045  %13 = add i16 %12, %cond14146  ret i16 %1347}48