570 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s3 4%v8i8 = type { i8, i8, i8, i8, i8, i8, i8, i8 }5 6; https://bugs.llvm.org/show_bug.cgi?id=431467 8define i64 @load_bswap(ptr %p) {9; CHECK-LABEL: @load_bswap(10; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 111; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 212; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 313; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 414; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 515; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 616; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 717; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 118; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 119; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 120; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 121; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 122; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 123; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 124; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 125; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i6426; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i6427; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i6428; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i6429; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i6430; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i6431; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i6432; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i6433; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 5634; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 4835; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 4036; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 3237; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 2438; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 1639; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 840; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]]41; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]]42; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]]43; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]44; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]45; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]46; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[Z7]]47; CHECK-NEXT: ret i64 [[OR01234567]]48;49 %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 150 %g2 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 251 %g3 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 352 %g4 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 453 %g5 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 554 %g6 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 655 %g7 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 756 57 %t0 = load i8, ptr %p58 %t1 = load i8, ptr %g159 %t2 = load i8, ptr %g260 %t3 = load i8, ptr %g361 %t4 = load i8, ptr %g462 %t5 = load i8, ptr %g563 %t6 = load i8, ptr %g664 %t7 = load i8, ptr %g765 66 %z0 = zext i8 %t0 to i6467 %z1 = zext i8 %t1 to i6468 %z2 = zext i8 %t2 to i6469 %z3 = zext i8 %t3 to i6470 %z4 = zext i8 %t4 to i6471 %z5 = zext i8 %t5 to i6472 %z6 = zext i8 %t6 to i6473 %z7 = zext i8 %t7 to i6474 75 %sh0 = shl nuw i64 %z0, 5676 %sh1 = shl nuw nsw i64 %z1, 4877 %sh2 = shl nuw nsw i64 %z2, 4078 %sh3 = shl nuw nsw i64 %z3, 3279 %sh4 = shl nuw nsw i64 %z4, 2480 %sh5 = shl nuw nsw i64 %z5, 1681 %sh6 = shl nuw nsw i64 %z6, 882; %sh7 = shl nuw nsw i64 %z7, 0 <-- missing phantom shift83 84 %or01 = or i64 %sh0, %sh185 %or012 = or i64 %or01, %sh286 %or0123 = or i64 %or012, %sh387 %or01234 = or i64 %or0123, %sh488 %or012345 = or i64 %or01234, %sh589 %or0123456 = or i64 %or012345, %sh690 %or01234567 = or i64 %or0123456, %z791 ret i64 %or0123456792}93 94define i64 @load_bswap_nop_shift(ptr %p) {95; CHECK-LABEL: @load_bswap_nop_shift(96; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 197; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 298; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 399; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4100; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5101; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6102; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7103; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 1104; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 1105; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 1106; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 1107; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 1108; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 1109; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 1110; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 1111; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64112; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64113; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64114; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64115; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64116; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64117; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64118; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64119; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56120; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48121; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40122; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32123; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24124; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16125; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8126; CHECK-NEXT: [[SH7:%.*]] = shl nuw nsw i64 [[Z7]], 0127; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]]128; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]]129; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]]130; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]131; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]132; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]133; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[SH7]]134; CHECK-NEXT: ret i64 [[OR01234567]]135;136 %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 1137 %g2 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 2138 %g3 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 3139 %g4 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 4140 %g5 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 5141 %g6 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 6142 %g7 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 7143 144 %t0 = load i8, ptr %p145 %t1 = load i8, ptr %g1146 %t2 = load i8, ptr %g2147 %t3 = load i8, ptr %g3148 %t4 = load i8, ptr %g4149 %t5 = load i8, ptr %g5150 %t6 = load i8, ptr %g6151 %t7 = load i8, ptr %g7152 153 %z0 = zext i8 %t0 to i64154 %z1 = zext i8 %t1 to i64155 %z2 = zext i8 %t2 to i64156 %z3 = zext i8 %t3 to i64157 %z4 = zext i8 %t4 to i64158 %z5 = zext i8 %t5 to i64159 %z6 = zext i8 %t6 to i64160 %z7 = zext i8 %t7 to i64161 162 %sh0 = shl nuw i64 %z0, 56163 %sh1 = shl nuw nsw i64 %z1, 48164 %sh2 = shl nuw nsw i64 %z2, 40165 %sh3 = shl nuw nsw i64 %z3, 32166 %sh4 = shl nuw nsw i64 %z4, 24167 %sh5 = shl nuw nsw i64 %z5, 16168 %sh6 = shl nuw nsw i64 %z6, 8169 %sh7 = shl nuw nsw i64 %z7, 0170 171 %or01 = or i64 %sh0, %sh1172 %or012 = or i64 %or01, %sh2173 %or0123 = or i64 %or012, %sh3174 %or01234 = or i64 %or0123, %sh4175 %or012345 = or i64 %or01234, %sh5176 %or0123456 = or i64 %or012345, %sh6177 %or01234567 = or i64 %or0123456, %sh7178 ret i64 %or01234567179}180 181; https://bugs.llvm.org/show_bug.cgi?id=42708182 183define i64 @load64le(ptr %arg) {184; CHECK-LABEL: @load64le(185; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1186; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2187; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3188; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4189; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5190; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6191; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7192; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1193; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1194; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1195; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1196; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1197; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1198; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1199; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1200; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64201; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64202; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64203; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64204; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64205; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64206; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64207; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64208; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8209; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16210; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24211; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32212; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40213; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48214; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56215; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[Z0]]216; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]]217; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]]218; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]]219; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]]220; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]]221; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]]222; CHECK-NEXT: ret i64 [[O7]]223;224 %g1 = getelementptr inbounds i8, ptr %arg, i64 1225 %g2 = getelementptr inbounds i8, ptr %arg, i64 2226 %g3 = getelementptr inbounds i8, ptr %arg, i64 3227 %g4 = getelementptr inbounds i8, ptr %arg, i64 4228 %g5 = getelementptr inbounds i8, ptr %arg, i64 5229 %g6 = getelementptr inbounds i8, ptr %arg, i64 6230 %g7 = getelementptr inbounds i8, ptr %arg, i64 7231 232 %ld0 = load i8, ptr %arg, align 1233 %ld1 = load i8, ptr %g1, align 1234 %ld2 = load i8, ptr %g2, align 1235 %ld3 = load i8, ptr %g3, align 1236 %ld4 = load i8, ptr %g4, align 1237 %ld5 = load i8, ptr %g5, align 1238 %ld6 = load i8, ptr %g6, align 1239 %ld7 = load i8, ptr %g7, align 1240 241 %z0 = zext i8 %ld0 to i64242 %z1 = zext i8 %ld1 to i64243 %z2 = zext i8 %ld2 to i64244 %z3 = zext i8 %ld3 to i64245 %z4 = zext i8 %ld4 to i64246 %z5 = zext i8 %ld5 to i64247 %z6 = zext i8 %ld6 to i64248 %z7 = zext i8 %ld7 to i64249 250; %s0 = shl nuw nsw i64 %z0, 0 <-- missing phantom shift251 %s1 = shl nuw nsw i64 %z1, 8252 %s2 = shl nuw nsw i64 %z2, 16253 %s3 = shl nuw nsw i64 %z3, 24254 %s4 = shl nuw nsw i64 %z4, 32255 %s5 = shl nuw nsw i64 %z5, 40256 %s6 = shl nuw nsw i64 %z6, 48257 %s7 = shl nuw i64 %z7, 56258 259 %o1 = or i64 %s1, %z0260 %o2 = or i64 %o1, %s2261 %o3 = or i64 %o2, %s3262 %o4 = or i64 %o3, %s4263 %o5 = or i64 %o4, %s5264 %o6 = or i64 %o5, %s6265 %o7 = or i64 %o6, %s7266 ret i64 %o7267}268 269define i64 @load64le_nop_shift(ptr %arg) {270; CHECK-LABEL: @load64le_nop_shift(271; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1272; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2273; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3274; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4275; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5276; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6277; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7278; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1279; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1280; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1281; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1282; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1283; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1284; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1285; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1286; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64287; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64288; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64289; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64290; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64291; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64292; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64293; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64294; CHECK-NEXT: [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 0295; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8296; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16297; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24298; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32299; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40300; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48301; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56302; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[S0]]303; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]]304; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]]305; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]]306; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]]307; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]]308; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]]309; CHECK-NEXT: ret i64 [[O7]]310;311 %g1 = getelementptr inbounds i8, ptr %arg, i64 1312 %g2 = getelementptr inbounds i8, ptr %arg, i64 2313 %g3 = getelementptr inbounds i8, ptr %arg, i64 3314 %g4 = getelementptr inbounds i8, ptr %arg, i64 4315 %g5 = getelementptr inbounds i8, ptr %arg, i64 5316 %g6 = getelementptr inbounds i8, ptr %arg, i64 6317 %g7 = getelementptr inbounds i8, ptr %arg, i64 7318 319 %ld0 = load i8, ptr %arg, align 1320 %ld1 = load i8, ptr %g1, align 1321 %ld2 = load i8, ptr %g2, align 1322 %ld3 = load i8, ptr %g3, align 1323 %ld4 = load i8, ptr %g4, align 1324 %ld5 = load i8, ptr %g5, align 1325 %ld6 = load i8, ptr %g6, align 1326 %ld7 = load i8, ptr %g7, align 1327 328 %z0 = zext i8 %ld0 to i64329 %z1 = zext i8 %ld1 to i64330 %z2 = zext i8 %ld2 to i64331 %z3 = zext i8 %ld3 to i64332 %z4 = zext i8 %ld4 to i64333 %z5 = zext i8 %ld5 to i64334 %z6 = zext i8 %ld6 to i64335 %z7 = zext i8 %ld7 to i64336 337 %s0 = shl nuw nsw i64 %z0, 0338 %s1 = shl nuw nsw i64 %z1, 8339 %s2 = shl nuw nsw i64 %z2, 16340 %s3 = shl nuw nsw i64 %z3, 24341 %s4 = shl nuw nsw i64 %z4, 32342 %s5 = shl nuw nsw i64 %z5, 40343 %s6 = shl nuw nsw i64 %z6, 48344 %s7 = shl nuw i64 %z7, 56345 346 %o1 = or i64 %s1, %s0347 %o2 = or i64 %o1, %s2348 %o3 = or i64 %o2, %s3349 %o4 = or i64 %o3, %s4350 %o5 = or i64 %o4, %s5351 %o6 = or i64 %o5, %s6352 %o7 = or i64 %o6, %s7353 ret i64 %o7354}355 356define void @PR39538(ptr %t0, ptr %t1) {357; CHECK-LABEL: @PR39538(358; CHECK-NEXT: [[T6:%.*]] = getelementptr inbounds i8, ptr [[T0:%.*]], i64 1359; CHECK-NEXT: [[T11:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 2360; CHECK-NEXT: [[T16:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 3361; CHECK-NEXT: [[T20:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 4362; CHECK-NEXT: [[T24:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 5363; CHECK-NEXT: [[T29:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 6364; CHECK-NEXT: [[T34:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 7365; CHECK-NEXT: [[T39:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 8366; CHECK-NEXT: [[T43:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 9367; CHECK-NEXT: [[T48:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 10368; CHECK-NEXT: [[T53:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 11369; CHECK-NEXT: [[T58:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 12370; CHECK-NEXT: [[T62:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 13371; CHECK-NEXT: [[T67:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 14372; CHECK-NEXT: [[T72:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 15373; CHECK-NEXT: [[T38:%.*]] = getelementptr inbounds i32, ptr [[T1:%.*]], i64 1374; CHECK-NEXT: [[T57:%.*]] = getelementptr inbounds i32, ptr [[T1]], i64 2375; CHECK-NEXT: [[T76:%.*]] = getelementptr inbounds i32, ptr [[T1]], i64 3376; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[T0]], align 1377; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[T6]], align 1378; CHECK-NEXT: [[T12:%.*]] = load i8, ptr [[T11]], align 1379; CHECK-NEXT: [[T17:%.*]] = load i8, ptr [[T16]], align 1380; CHECK-NEXT: [[T21:%.*]] = load i8, ptr [[T20]], align 1381; CHECK-NEXT: [[T25:%.*]] = load i8, ptr [[T24]], align 1382; CHECK-NEXT: [[T30:%.*]] = load i8, ptr [[T29]], align 1383; CHECK-NEXT: [[T35:%.*]] = load i8, ptr [[T34]], align 1384; CHECK-NEXT: [[T40:%.*]] = load i8, ptr [[T39]], align 1385; CHECK-NEXT: [[T44:%.*]] = load i8, ptr [[T43]], align 1386; CHECK-NEXT: [[T49:%.*]] = load i8, ptr [[T48]], align 1387; CHECK-NEXT: [[T54:%.*]] = load i8, ptr [[T53]], align 1388; CHECK-NEXT: [[T59:%.*]] = load i8, ptr [[T58]], align 1389; CHECK-NEXT: [[T63:%.*]] = load i8, ptr [[T62]], align 1390; CHECK-NEXT: [[T68:%.*]] = load i8, ptr [[T67]], align 1391; CHECK-NEXT: [[T73:%.*]] = load i8, ptr [[T72]], align 1392; CHECK-NEXT: [[T4:%.*]] = zext i8 [[T3]] to i32393; CHECK-NEXT: [[T8:%.*]] = zext i8 [[T7]] to i32394; CHECK-NEXT: [[T13:%.*]] = zext i8 [[T12]] to i32395; CHECK-NEXT: [[T18:%.*]] = zext i8 [[T17]] to i32396; CHECK-NEXT: [[T22:%.*]] = zext i8 [[T21]] to i32397; CHECK-NEXT: [[T26:%.*]] = zext i8 [[T25]] to i32398; CHECK-NEXT: [[T31:%.*]] = zext i8 [[T30]] to i32399; CHECK-NEXT: [[T36:%.*]] = zext i8 [[T35]] to i32400; CHECK-NEXT: [[T41:%.*]] = zext i8 [[T40]] to i32401; CHECK-NEXT: [[T45:%.*]] = zext i8 [[T44]] to i32402; CHECK-NEXT: [[T50:%.*]] = zext i8 [[T49]] to i32403; CHECK-NEXT: [[T55:%.*]] = zext i8 [[T54]] to i32404; CHECK-NEXT: [[T60:%.*]] = zext i8 [[T59]] to i32405; CHECK-NEXT: [[T64:%.*]] = zext i8 [[T63]] to i32406; CHECK-NEXT: [[T69:%.*]] = zext i8 [[T68]] to i32407; CHECK-NEXT: [[T74:%.*]] = zext i8 [[T73]] to i32408; CHECK-NEXT: [[T5:%.*]] = shl nuw i32 [[T4]], 24409; CHECK-NEXT: [[T23:%.*]] = shl nuw i32 [[T22]], 24410; CHECK-NEXT: [[T42:%.*]] = shl nuw i32 [[T41]], 24411; CHECK-NEXT: [[T61:%.*]] = shl nuw i32 [[T60]], 24412; CHECK-NEXT: [[T9:%.*]] = shl nuw nsw i32 [[T8]], 16413; CHECK-NEXT: [[T27:%.*]] = shl nuw nsw i32 [[T26]], 16414; CHECK-NEXT: [[T46:%.*]] = shl nuw nsw i32 [[T45]], 16415; CHECK-NEXT: [[T65:%.*]] = shl nuw nsw i32 [[T64]], 16416; CHECK-NEXT: [[T14:%.*]] = shl nuw nsw i32 [[T13]], 8417; CHECK-NEXT: [[T32:%.*]] = shl nuw nsw i32 [[T31]], 8418; CHECK-NEXT: [[T51:%.*]] = shl nuw nsw i32 [[T50]], 8419; CHECK-NEXT: [[T70:%.*]] = shl nuw nsw i32 [[T69]], 8420; CHECK-NEXT: [[T10:%.*]] = or i32 [[T9]], [[T5]]421; CHECK-NEXT: [[T15:%.*]] = or i32 [[T10]], [[T14]]422; CHECK-NEXT: [[T19:%.*]] = or i32 [[T15]], [[T18]]423; CHECK-NEXT: [[T28:%.*]] = or i32 [[T27]], [[T23]]424; CHECK-NEXT: [[T33:%.*]] = or i32 [[T28]], [[T32]]425; CHECK-NEXT: [[T37:%.*]] = or i32 [[T33]], [[T36]]426; CHECK-NEXT: [[T47:%.*]] = or i32 [[T46]], [[T42]]427; CHECK-NEXT: [[T52:%.*]] = or i32 [[T47]], [[T51]]428; CHECK-NEXT: [[T56:%.*]] = or i32 [[T52]], [[T55]]429; CHECK-NEXT: [[T66:%.*]] = or i32 [[T65]], [[T61]]430; CHECK-NEXT: [[T71:%.*]] = or i32 [[T66]], [[T70]]431; CHECK-NEXT: [[T75:%.*]] = or i32 [[T71]], [[T74]]432; CHECK-NEXT: store i32 [[T19]], ptr [[T1]], align 4433; CHECK-NEXT: store i32 [[T37]], ptr [[T38]], align 4434; CHECK-NEXT: store i32 [[T56]], ptr [[T57]], align 4435; CHECK-NEXT: store i32 [[T75]], ptr [[T76]], align 4436; CHECK-NEXT: ret void437;438 %t6 = getelementptr inbounds i8, ptr %t0, i64 1439 %t11 = getelementptr inbounds i8, ptr %t0, i64 2440 %t16 = getelementptr inbounds i8, ptr %t0, i64 3441 %t20 = getelementptr inbounds i8, ptr %t0, i64 4442 %t24 = getelementptr inbounds i8, ptr %t0, i64 5443 %t29 = getelementptr inbounds i8, ptr %t0, i64 6444 %t34 = getelementptr inbounds i8, ptr %t0, i64 7445 %t39 = getelementptr inbounds i8, ptr %t0, i64 8446 %t43 = getelementptr inbounds i8, ptr %t0, i64 9447 %t48 = getelementptr inbounds i8, ptr %t0, i64 10448 %t53 = getelementptr inbounds i8, ptr %t0, i64 11449 %t58 = getelementptr inbounds i8, ptr %t0, i64 12450 %t62 = getelementptr inbounds i8, ptr %t0, i64 13451 %t67 = getelementptr inbounds i8, ptr %t0, i64 14452 %t72 = getelementptr inbounds i8, ptr %t0, i64 15453 %t38 = getelementptr inbounds i32, ptr %t1, i64 1454 %t57 = getelementptr inbounds i32, ptr %t1, i64 2455 %t76 = getelementptr inbounds i32, ptr %t1, i64 3456 %t3 = load i8, ptr %t0, align 1457 %t7 = load i8, ptr %t6, align 1458 %t12 = load i8, ptr %t11, align 1459 %t17 = load i8, ptr %t16, align 1460 %t21 = load i8, ptr %t20, align 1461 %t25 = load i8, ptr %t24, align 1462 %t30 = load i8, ptr %t29, align 1463 %t35 = load i8, ptr %t34, align 1464 %t40 = load i8, ptr %t39, align 1465 %t44 = load i8, ptr %t43, align 1466 %t49 = load i8, ptr %t48, align 1467 %t54 = load i8, ptr %t53, align 1468 %t59 = load i8, ptr %t58, align 1469 %t63 = load i8, ptr %t62, align 1470 %t68 = load i8, ptr %t67, align 1471 %t73 = load i8, ptr %t72, align 1472 %t4 = zext i8 %t3 to i32473 %t8 = zext i8 %t7 to i32474 %t13 = zext i8 %t12 to i32475 %t18 = zext i8 %t17 to i32476 %t22 = zext i8 %t21 to i32477 %t26 = zext i8 %t25 to i32478 %t31 = zext i8 %t30 to i32479 %t36 = zext i8 %t35 to i32480 %t41 = zext i8 %t40 to i32481 %t45 = zext i8 %t44 to i32482 %t50 = zext i8 %t49 to i32483 %t55 = zext i8 %t54 to i32484 %t60 = zext i8 %t59 to i32485 %t64 = zext i8 %t63 to i32486 %t69 = zext i8 %t68 to i32487 %t74 = zext i8 %t73 to i32488 %t5 = shl nuw i32 %t4, 24489 %t23 = shl nuw i32 %t22, 24490 %t42 = shl nuw i32 %t41, 24491 %t61 = shl nuw i32 %t60, 24492 %t9 = shl nuw nsw i32 %t8, 16493 %t27 = shl nuw nsw i32 %t26, 16494 %t46 = shl nuw nsw i32 %t45, 16495 %t65 = shl nuw nsw i32 %t64, 16496 %t14 = shl nuw nsw i32 %t13, 8497 %t32 = shl nuw nsw i32 %t31, 8498 %t51 = shl nuw nsw i32 %t50, 8499 %t70 = shl nuw nsw i32 %t69, 8500 %t10 = or i32 %t9, %t5501 %t15 = or i32 %t10, %t14502 %t19 = or i32 %t15, %t18503 %t28 = or i32 %t27, %t23504 %t33 = or i32 %t28, %t32505 %t37 = or i32 %t33, %t36506 %t47 = or i32 %t46, %t42507 %t52 = or i32 %t47, %t51508 %t56 = or i32 %t52, %t55509 %t66 = or i32 %t65, %t61510 %t71 = or i32 %t66, %t70511 %t75 = or i32 %t71, %t74512 store i32 %t19, ptr %t1, align 4513 store i32 %t37, ptr %t38, align 4514 store i32 %t56, ptr %t57, align 4515 store i32 %t75, ptr %t76, align 4516 ret void517}518 519; Do not crash on constant expressions.520 521@g1 = external dso_local unnamed_addr constant [8 x i8], align 1522@g2 = external dso_local unnamed_addr constant [5 x i8], align 1523 524define void @load_combine_constant_expression(ptr %t1) {525; CHECK-LABEL: @load_combine_constant_expression(526; CHECK-NEXT: [[EXT1:%.*]] = zext i32 ptrtoint (ptr @g1 to i32) to i64527; CHECK-NEXT: [[EXT2:%.*]] = zext i32 ptrtoint (ptr @g2 to i32) to i64528; CHECK-NEXT: [[SHL1:%.*]] = shl i64 [[EXT1]], 32529; CHECK-NEXT: [[OR1:%.*]] = or i64 [[SHL1]], [[EXT2]]530; CHECK-NEXT: store i64 [[OR1]], ptr [[T1:%.*]], align 4531; CHECK-NEXT: [[T3:%.*]] = getelementptr i64, ptr [[T1]], i64 1532; CHECK-NEXT: [[SHL2:%.*]] = shl i64 [[EXT1]], 32533; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SHL2]], [[EXT2]]534; CHECK-NEXT: store i64 [[OR2]], ptr [[T3]], align 4535; CHECK-NEXT: ret void536;537 %ext1 = zext i32 ptrtoint (ptr @g1 to i32) to i64538 %ext2 = zext i32 ptrtoint (ptr @g2 to i32) to i64539 %shl1 = shl i64 %ext1, 32540 %or1 = or i64 %shl1, %ext2541 store i64 %or1, ptr %t1, align 4542 %t3 = getelementptr i64, ptr %t1, i64 1543 %shl2 = shl i64 %ext1, 32544 %or2 = or i64 %shl2, %ext2545 store i64 %or2, ptr %t3, align 4546 ret void547}548 549@output = dso_local local_unnamed_addr global [8 x i32] zeroinitializer, align 16550 551define void @PR47450(ptr nocapture readonly %p) {552; CHECK-LABEL: @PR47450(553; CHECK-NEXT: [[X:%.*]] = load i16, ptr [[P:%.*]], align 2554; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X]] to i32555; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 1556; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i32 0557; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer558; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @output, align 16559; CHECK-NEXT: ret void560;561 %x = load i16, ptr %p, align 2562 %z = zext i16 %x to i32563 %s = shl nuw nsw i32 %z, 1564 store i32 %s, ptr @output, align 16565 store i32 %s, ptr getelementptr inbounds ([8 x i32], ptr @output, i64 0, i64 1), align 4566 store i32 %s, ptr getelementptr inbounds ([8 x i32], ptr @output, i64 0, i64 2), align 8567 store i32 %s, ptr getelementptr inbounds ([8 x i32], ptr @output, i64 0, i64 3), align 4568 ret void569}570