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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -slp-threshold=-999 < %s | FileCheck %s3 4 5; S[0] = %v1 + %v26; S[1] = %v2 + %v17; S[2] = %v2 + %v18; S[3] = %v1 + %v29;10; We broadcast %v1 and %v211;12 13define void @bcast_vals(ptr %A, ptr %B, ptr %S) {14; CHECK-LABEL: @bcast_vals(15; CHECK-NEXT: entry:16; CHECK-NEXT: [[A0:%.*]] = load i64, ptr [[A:%.*]], align 817; CHECK-NEXT: [[B0:%.*]] = load i64, ptr [[B:%.*]], align 818; CHECK-NEXT: [[V1:%.*]] = sub i64 [[A0]], 119; CHECK-NEXT: [[V2:%.*]] = sub i64 [[B0]], 120; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[V1]], i32 021; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <4 x i32> zeroinitializer22; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> poison, i64 [[V2]], i32 023; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> zeroinitializer24; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP1]], [[TMP3]]25; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr [[S:%.*]], align 826; CHECK-NEXT: ret void27;28entry:29 %A0 = load i64, ptr %A, align 830 %B0 = load i64, ptr %B, align 831 32 %v1 = sub i64 %A0, 133 %v2 = sub i64 %B0, 134 35 %Add0 = add i64 %v1, %v236 %Add1 = add i64 %v2, %v137 %Add2 = add i64 %v2, %v138 %Add3 = add i64 %v1, %v239 40 %idxS1 = getelementptr inbounds i64, ptr %S, i64 141 %idxS2 = getelementptr inbounds i64, ptr %S, i64 242 %idxS3 = getelementptr inbounds i64, ptr %S, i64 343 44 store i64 %Add0, ptr %S, align 845 store i64 %Add1, ptr %idxS1, align 846 store i64 %Add2, ptr %idxS2, align 847 store i64 %Add3, ptr %idxS3, align 848 ret void49}50 51; S[0] = %v1 + %v252; S[1] = %v3 + %v153; S[2] = %v5 + %v154; S[3] = %v1 + %v455;56; We broadcast %v1.57 58;59define void @bcast_vals2(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %S) {60; CHECK-LABEL: @bcast_vals2(61; CHECK-NEXT: entry:62; CHECK-NEXT: [[A0:%.*]] = load i16, ptr [[A:%.*]], align 863; CHECK-NEXT: [[B0:%.*]] = load i16, ptr [[B:%.*]], align 864; CHECK-NEXT: [[C0:%.*]] = load i16, ptr [[C:%.*]], align 865; CHECK-NEXT: [[D0:%.*]] = load i16, ptr [[D:%.*]], align 866; CHECK-NEXT: [[E0:%.*]] = load i16, ptr [[E:%.*]], align 867; CHECK-NEXT: [[V1:%.*]] = sext i16 [[A0]] to i3268; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[B0]], i32 069; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[C0]], i32 170; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[E0]], i32 271; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[D0]], i32 372; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i16> [[TMP3]] to <4 x i32>73; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[V1]], i32 074; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <4 x i32> zeroinitializer75; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i32> [[TMP6]], [[TMP4]]76; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr [[S:%.*]], align 877; CHECK-NEXT: ret void78;79entry:80 %A0 = load i16, ptr %A, align 881 %B0 = load i16, ptr %B, align 882 %C0 = load i16, ptr %C, align 883 %D0 = load i16, ptr %D, align 884 %E0 = load i16, ptr %E, align 885 86 %v1 = sext i16 %A0 to i3287 %v2 = sext i16 %B0 to i3288 %v3 = sext i16 %C0 to i3289 %v4 = sext i16 %D0 to i3290 %v5 = sext i16 %E0 to i3291 92 %Add0 = add i32 %v1, %v293 %Add1 = add i32 %v3, %v194 %Add2 = add i32 %v5, %v195 %Add3 = add i32 %v1, %v496 97 %idxS1 = getelementptr inbounds i32, ptr %S, i64 198 %idxS2 = getelementptr inbounds i32, ptr %S, i64 299 %idxS3 = getelementptr inbounds i32, ptr %S, i64 3100 101 store i32 %Add0, ptr %S, align 8102 store i32 %Add1, ptr %idxS1, align 8103 store i32 %Add2, ptr %idxS2, align 8104 store i32 %Add3, ptr %idxS3, align 8105 ret void106}107