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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -passes=slp-vectorizer -mtriple=-x86_64-grtev4-linux-gnu -S -mcpu=corei7-avx -pass-remarks-output=%t < %s | FileCheck %s3; RUN: FileCheck --input-file=%t --check-prefix=YAML %s4 5; Building a vector of a float (lane 0) and an extract from lane 1 (lane 1)6; should have a cost of +1 because we need an extra instruction to combine7; both into a single vector.8; So this code should not be vectorized.9 10; YAML: --- !Missed11; YAML: Pass: slp-vectorizer12; YAML: Name: NotBeneficial13; YAML: Function: test14; YAML: Args:15; YAML: - String: 'List vectorization was possible but not beneficial with cost '16; YAML: - Cost: '0'17; YAML: - String: ' >= '18; YAML: - Treshold: '0'19; YAML: ...20define void @test(<4 x float> %vec, float %a, float %b, ptr %ptr) {21; CHECK-LABEL: define void @test22; CHECK-SAME: (<4 x float> [[VEC:%.*]], float [[A:%.*]], float [[B:%.*]], ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {23; CHECK-NEXT: [[FADD:%.*]] = fadd float [[A]], [[B]]24; CHECK-NEXT: [[EXTR1:%.*]] = extractelement <4 x float> [[VEC]], i64 125; CHECK-NEXT: [[FSUB0:%.*]] = fsub float [[FADD]], [[FADD]]26; CHECK-NEXT: [[FSUB1:%.*]] = fsub float [[EXTR1]], [[EXTR1]]27; CHECK-NEXT: [[ROOT:%.*]] = fadd float [[FSUB0]], [[FSUB1]]28; CHECK-NEXT: store float [[ROOT]], ptr [[PTR]], align 429; CHECK-NEXT: ret void30;31 %fadd = fadd float %a, %b32 %extr1 = extractelement <4 x float> %vec, i64 133 34 %fsub0 = fsub float %fadd, %fadd35 %fsub1 = fsub float %extr1, %extr136 37 %root = fadd float %fsub0, %fsub138 store float %root, ptr %ptr39 ret void40}41