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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2;RUN: opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-android23 < %s | FileCheck %s3 4define void @test() {5; CHECK-LABEL: @test(6; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 27; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 48; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 49; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]10; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 011; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 112; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]13; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 014; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 415; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <2 x i32> <i32 1, i32 poison>16; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 417; CHECK-NEXT: ret void18;19 %1 = getelementptr inbounds float, ptr undef, i32 220 %2 = load float, ptr %1, align 421 %3 = load float, ptr undef, align 422 %4 = fsub float %2, %323 %5 = getelementptr inbounds float, ptr undef, i32 324 %6 = load float, ptr %5, align 425 %7 = getelementptr inbounds float, ptr undef, i32 126 %8 = load float, ptr %7, align 427 %9 = fsub float %6, %828 %10 = fcmp olt float %9, %429 %11 = insertelement <2 x float> undef, float %3, i64 030 %12 = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 031 store <2 x float> zeroinitializer, ptr null, align 432 %13 = insertelement <2 x float> %11, float %6, i64 033 store <2 x float> zeroinitializer, ptr null, align 434 ret void35}36 37define void @test1() {38; CHECK-LABEL: @test1(39; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 240; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 441; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 442; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]43; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 044; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 145; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]46; CHECK-NEXT: store <2 x float> [[TMP3]], ptr null, align 447; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP2]], <2 x i32> <i32 0, i32 3>48; CHECK-NEXT: store <2 x float> [[TMP8]], ptr null, align 449; CHECK-NEXT: ret void50;51 %1 = getelementptr inbounds float, ptr undef, i32 252 %2 = load float, ptr %1, align 453 %3 = load float, ptr undef, align 454 %4 = fsub float %2, %355 %5 = getelementptr inbounds float, ptr undef, i32 356 %6 = load float, ptr %5, align 457 %7 = getelementptr inbounds float, ptr undef, i32 158 %8 = load float, ptr %7, align 459 %9 = fsub float %6, %860 %10 = fcmp olt float %9, %461 %.sroa.0.0.vec.insert.i5.i10 = insertelement <2 x float> undef, float %3, i64 062 %.sroa.0.4.vec.insert.i10.i13 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %8, i64 163 store <2 x float> %.sroa.0.4.vec.insert.i10.i13, ptr null, align 464 %.sroa.0.4.vec.insert.i10.i13.2 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %6, i64 165 store <2 x float> %.sroa.0.4.vec.insert.i10.i13.2, ptr null, align 466 ret void67}68 69