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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7 -passes=slp-vectorizer,dce -S | FileCheck %s --check-prefixes=CHECK,SSE423; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -passes=slp-vectorizer,dce -S | FileCheck %s --check-prefixes=CHECK,AVX4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"6 7; int test_sext_4i8_to_4i32(int * restrict A, char * restrict B) {8; A[0] = B[0];9; A[1] = B[1];10; A[2] = B[2];11; A[3] = B[3];12; }13 14define i32 @test_sext_4i8_to_4i32(ptr noalias nocapture %A, ptr noalias nocapture %B) {15; CHECK-LABEL: @test_sext_4i8_to_4i32(16; CHECK-NEXT: entry:17; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[B:%.*]], align 118; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i32>19; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[A:%.*]], align 420; CHECK-NEXT: ret i32 undef21;22entry:23 %0 = load i8, ptr %B, align 124 %conv = sext i8 %0 to i3225 store i32 %conv, ptr %A, align 426 %arrayidx2 = getelementptr inbounds i8, ptr %B, i64 127 %1 = load i8, ptr %arrayidx2, align 128 %conv3 = sext i8 %1 to i3229 %arrayidx4 = getelementptr inbounds i32, ptr %A, i64 130 store i32 %conv3, ptr %arrayidx4, align 431 %arrayidx5 = getelementptr inbounds i8, ptr %B, i64 232 %2 = load i8, ptr %arrayidx5, align 133 %conv6 = sext i8 %2 to i3234 %arrayidx7 = getelementptr inbounds i32, ptr %A, i64 235 store i32 %conv6, ptr %arrayidx7, align 436 %arrayidx8 = getelementptr inbounds i8, ptr %B, i64 337 %3 = load i8, ptr %arrayidx8, align 138 %conv9 = sext i8 %3 to i3239 %arrayidx10 = getelementptr inbounds i32, ptr %A, i64 340 store i32 %conv9, ptr %arrayidx10, align 441 ret i32 undef42}43 44define i32 @test_zext_4i16_to_4i32(ptr noalias nocapture %A, ptr noalias nocapture %B) {45; CHECK-LABEL: @test_zext_4i16_to_4i32(46; CHECK-NEXT: entry:47; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[B:%.*]], align 148; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>49; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[A:%.*]], align 450; CHECK-NEXT: ret i32 undef51;52entry:53 %0 = load i16, ptr %B, align 154 %conv = zext i16 %0 to i3255 store i32 %conv, ptr %A, align 456 %arrayidx2 = getelementptr inbounds i16, ptr %B, i64 157 %1 = load i16, ptr %arrayidx2, align 158 %conv3 = zext i16 %1 to i3259 %arrayidx4 = getelementptr inbounds i32, ptr %A, i64 160 store i32 %conv3, ptr %arrayidx4, align 461 %arrayidx5 = getelementptr inbounds i16, ptr %B, i64 262 %2 = load i16, ptr %arrayidx5, align 163 %conv6 = zext i16 %2 to i3264 %arrayidx7 = getelementptr inbounds i32, ptr %A, i64 265 store i32 %conv6, ptr %arrayidx7, align 466 %arrayidx8 = getelementptr inbounds i16, ptr %B, i64 367 %3 = load i16, ptr %arrayidx8, align 168 %conv9 = zext i16 %3 to i3269 %arrayidx10 = getelementptr inbounds i32, ptr %A, i64 370 store i32 %conv9, ptr %arrayidx10, align 471 ret i32 undef72}73 74define i64 @test_sext_4i16_to_4i64(ptr noalias nocapture %A, ptr noalias nocapture %B) {75; SSE42-LABEL: @test_sext_4i16_to_4i64(76; SSE42-NEXT: entry:77; SSE42-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[B:%.*]], align 178; SSE42-NEXT: [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i64>79; SSE42-NEXT: store <2 x i64> [[TMP2]], ptr [[A:%.*]], align 480; SSE42-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[B]], i64 281; SSE42-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 282; SSE42-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr [[ARRAYIDX5]], align 183; SSE42-NEXT: [[TMP6:%.*]] = sext <2 x i16> [[TMP5]] to <2 x i64>84; SSE42-NEXT: store <2 x i64> [[TMP6]], ptr [[ARRAYIDX7]], align 485; SSE42-NEXT: ret i64 undef86;87; AVX-LABEL: @test_sext_4i16_to_4i64(88; AVX-NEXT: entry:89; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[B:%.*]], align 190; AVX-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i64>91; AVX-NEXT: store <4 x i64> [[TMP2]], ptr [[A:%.*]], align 492; AVX-NEXT: ret i64 undef93;94entry:95 %0 = load i16, ptr %B, align 196 %conv = sext i16 %0 to i6497 store i64 %conv, ptr %A, align 498 %arrayidx2 = getelementptr inbounds i16, ptr %B, i64 199 %1 = load i16, ptr %arrayidx2, align 1100 %conv3 = sext i16 %1 to i64101 %arrayidx4 = getelementptr inbounds i64, ptr %A, i64 1102 store i64 %conv3, ptr %arrayidx4, align 4103 %arrayidx5 = getelementptr inbounds i16, ptr %B, i64 2104 %2 = load i16, ptr %arrayidx5, align 1105 %conv6 = sext i16 %2 to i64106 %arrayidx7 = getelementptr inbounds i64, ptr %A, i64 2107 store i64 %conv6, ptr %arrayidx7, align 4108 %arrayidx8 = getelementptr inbounds i16, ptr %B, i64 3109 %3 = load i16, ptr %arrayidx8, align 1110 %conv9 = sext i16 %3 to i64111 %arrayidx10 = getelementptr inbounds i64, ptr %A, i64 3112 store i64 %conv9, ptr %arrayidx10, align 4113 ret i64 undef114}115