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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -mcpu=skx -S -o - -mtriple=x86_64-unknown < %s | FileCheck %s3 4define void @test(ptr %0, double %1) {5; CHECK-LABEL: @test(6; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[TMP0:%.*]], i32 67; CHECK-NEXT: br label [[TMP4:%.*]]8; CHECK: 4:9; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP1:%.*]], i32 110; CHECK-NEXT: br label [[TMP6:%.*]]11; CHECK: 6:12; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr null, align 813; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP7]], i32 114; CHECK-NEXT: [[TMP9:%.*]] = fcmp olt <2 x double> [[TMP5]], [[TMP8]]15; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP9]], <2 x double> zeroinitializer, <2 x double> zeroinitializer16; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP10]], zeroinitializer17; CHECK-NEXT: [[TMP12:%.*]] = fadd <2 x double> zeroinitializer, [[TMP11]]18; CHECK-NEXT: store <2 x double> [[TMP12]], ptr [[TMP3]], align 819; CHECK-NEXT: br label [[TMP6]]20;21 %3 = getelementptr inbounds double, ptr %0, i32 622 %4 = getelementptr inbounds double, ptr %0, i32 723 br label %524 255: ; preds = %226 br label %627 286: ; preds = %6, %529 %7 = load double, ptr null, align 830 %8 = fcmp olt double 0.000000e+00, 0.000000e+0031 %9 = select i1 %8, double 0.000000e+00, double 0.000000e+0032 %10 = fcmp ogt double %7, %133 %11 = select i1 %10, double 0.000000e+00, double 0.000000e+0034 %12 = fmul double %9, 0.000000e+0035 %13 = fmul double 0.000000e+00, %1136 %14 = fadd double 0.000000e+00, %1237 store double %14, ptr %3, align 838 %15 = fadd double 0.000000e+00, %1339 store double %15, ptr %4, align 840 br label %641}42 43define { <2 x float>, <2 x float> } @test1(i32 %conv.i32.i.i.i) {44; CHECK-LABEL: @test1(45; CHECK-NEXT: entry:46; CHECK-NEXT: [[CONV_I32_I_I_I1:%.*]] = fptosi float 0.000000e+00 to i3247; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, i32 [[CONV_I32_I_I_I:%.*]], i32 048; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CONV_I32_I_I_I1]], i32 249; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[TMP1]], zeroinitializer50; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP1]], zeroinitializer51; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>52; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP4]], <4 x float> zeroinitializer, <4 x float> zeroinitializer53; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[TMP5]], zeroinitializer54; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> poison, <2 x i32> <i32 0, i32 1>55; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> poison, <2 x i32> <i32 2, i32 3>56; CHECK-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } zeroinitializer, <2 x float> [[TMP7]], 057; CHECK-NEXT: [[DOTFCA_1_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } [[DOTFCA_0_INSERT]], <2 x float> [[TMP8]], 158; CHECK-NEXT: ret { <2 x float>, <2 x float> } zeroinitializer59;60entry:61 %cmp.i.i.i.i.i = icmp slt i32 0, 062 %cond.i.i.i.i = select i1 %cmp.i.i.i.i.i, float 0.000000e+00, float 0.000000e+0063 %conv.i32.i.i.i1 = fptosi float 0.000000e+00 to i3264 %cmp.i.i34.i.i.i = icmp slt i32 %conv.i32.i.i.i1, 065 %cond.i35.i.i.i = select i1 %cmp.i.i34.i.i.i, float 0.000000e+00, float 0.000000e+0066 %cmp.i.i38.i.i.i = icmp sgt i32 0, 067 %cond.i39.i.i.i = select i1 %cmp.i.i38.i.i.i, float 0.000000e+00, float 0.000000e+0068 %cmp.i.i42.i.i.i = icmp sgt i32 %conv.i32.i.i.i, 069 %cond.i43.i.i.i = select i1 %cmp.i.i42.i.i.i, float 0.000000e+00, float 0.000000e+0070 %add.i.i = fadd float 0.000000e+00, 0.000000e+0071 %add4.i.i = fadd float 0.000000e+00, 0.000000e+0072 %add.i9.i = fadd float %cond.i43.i.i.i, %add.i.i73 %retval.sroa.0.0.vec.insert4 = insertelement <2 x float> zeroinitializer, float %add.i9.i, i64 074 %add4.i12.i = fadd float %cond.i39.i.i.i, %add4.i.i75 %retval.sroa.0.4.vec.insert7 = insertelement <2 x float> %retval.sroa.0.0.vec.insert4, float %add4.i12.i, i64 176 %add.i15.i = fadd float %cond.i35.i.i.i, %add.i.i77 %retval.sroa.7.8.vec.insert11 = insertelement <2 x float> zeroinitializer, float %add.i15.i, i64 078 %add4.i18.i = fadd float %cond.i.i.i.i, %add4.i.i79 %retval.sroa.7.12.vec.insert13 = insertelement <2 x float> %retval.sroa.7.8.vec.insert11, float %add4.i18.i, i64 180 %.fca.0.insert = insertvalue { <2 x float>, <2 x float> } zeroinitializer, <2 x float> %retval.sroa.0.4.vec.insert7, 081 %.fca.1.insert = insertvalue { <2 x float>, <2 x float> } %.fca.0.insert, <2 x float> %retval.sroa.7.12.vec.insert13, 182 ret { <2 x float>, <2 x float> } zeroinitializer83}84