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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-100 < %s | FileCheck %s3 4define i8 @test(ptr %g_127, i32 %0, i16 %1) {5; CHECK-LABEL: define i8 @test(6; CHECK-SAME: ptr [[G_127:%.*]], i32 [[TMP0:%.*]], i16 [[TMP1:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: br label %[[FOR_INC434_I:.*]]9; CHECK: [[FOR_COND166_PREHEADER_I:.*]]:10; CHECK-NEXT: br label %[[FOR_INC434_I]]11; CHECK: [[FOR_INC434_I]]:12; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 60, %[[FOR_COND166_PREHEADER_I]] ]13; CHECK-NEXT: [[CONV8_I_I:%.*]] = zext nneg i32 [[TMP0]] to i6414; CHECK-NEXT: [[DIV_I_I_1:%.*]] = udiv i64 [[CONV8_I_I]], [[TMP2]]15; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DIV_I_I_1]] to i1616; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> poison, i16 [[TMP3]], i32 017; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> poison, i64 [[CONV8_I_I]], i32 018; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> zeroinitializer19; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i32 020; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> zeroinitializer21; CHECK-NEXT: [[TMP9:%.*]] = udiv <4 x i64> [[TMP6]], [[TMP8]]22; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i16>23; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i16> [[TMP10]], <4 x i16> poison, <8 x i32> <i32 0, i32 poison, i32 1, i32 2, i32 poison, i32 3, i32 poison, i32 poison>24; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i16> [[TMP4]], <8 x i16> [[TMP11]], <8 x i32> <i32 0, i32 8, i32 poison, i32 10, i32 11, i32 poison, i32 13, i32 poison>25; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[TMP12]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 4, i32 6, i32 6>26; CHECK-NEXT: [[TMP14:%.*]] = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> [[TMP13]])27; CHECK-NEXT: [[TMP15:%.*]] = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> [[TMP14]])28; CHECK-NEXT: [[OP_RDX:%.*]] = and i16 [[TMP15]], [[TMP1]]29; CHECK-NEXT: [[AND14_I_2_I_5:%.*]] = zext i16 [[OP_RDX]] to i3230; CHECK-NEXT: store i32 [[AND14_I_2_I_5]], ptr [[G_127]], align 431; CHECK-NEXT: ret i8 032;33entry:34 br label %for.inc434.i35 36for.cond166.preheader.i:37 br label %for.inc434.i38 39for.inc434.i:40 %2 = phi i64 [ 0, %entry ], [ 60, %for.cond166.preheader.i ]41 %conv8.i.i = zext nneg i32 %0 to i6442 %div.i.i.1 = udiv i64 %conv8.i.i, %243 %3 = trunc i64 %div.i.i.1 to i1644 %call12.i.2.i.1 = tail call i16 @llvm.bswap.i16(i16 %3)45 %and14.i.2.i.118 = and i16 %1, %call12.i.2.i.146 %div.i.i.2 = udiv i64 %conv8.i.i, %247 %4 = trunc i64 %div.i.i.2 to i1648 %call12.i.i.2 = tail call i16 @llvm.bswap.i16(i16 %4)49 %and14.i.i.219 = and i16 %and14.i.2.i.118, %call12.i.i.250 %call12.i.2.i.2 = tail call i16 @llvm.bswap.i16(i16 %4)51 %and14.i.2.i.220 = and i16 %and14.i.i.219, %call12.i.2.i.252 %div.i.i.3 = udiv i64 %conv8.i.i, %253 %5 = trunc i64 %div.i.i.3 to i1654 %call12.i.2.i.3 = tail call i16 @llvm.bswap.i16(i16 %5)55 %and14.i.2.i.322 = and i16 %and14.i.2.i.220, %call12.i.2.i.356 %div.i.i.4 = udiv i64 %conv8.i.i, %257 %6 = trunc i64 %div.i.i.4 to i1658 %call12.i.i.4 = tail call i16 @llvm.bswap.i16(i16 %6)59 %and14.i.i.423 = and i16 %and14.i.2.i.322, %call12.i.i.460 %call12.i.2.i.4 = tail call i16 @llvm.bswap.i16(i16 %6)61 %and14.i.2.i.424 = and i16 %and14.i.i.423, %call12.i.2.i.462 %div.i.i.5 = udiv i64 %conv8.i.i, %263 %7 = trunc i64 %div.i.i.5 to i1664 %call12.i.i.5 = tail call i16 @llvm.bswap.i16(i16 %7)65 %and14.i.i.525 = and i16 %and14.i.2.i.424, %call12.i.i.566 %call12.i.2.i.5 = tail call i16 @llvm.bswap.i16(i16 %7)67 %and14.i.2.i.51 = and i16 %and14.i.i.525, %call12.i.2.i.568 %and14.i.2.i.5 = zext i16 %and14.i.2.i.51 to i3269 store i32 %and14.i.2.i.5, ptr %g_127, align 470 ret i8 071}72