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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-generic-linux-gnu < %s | FileCheck %s3 4define void @test(ptr %nExp, float %0, i1 %cmp, float %1) {5; CHECK-LABEL: define void @test(6; CHECK-SAME: ptr [[NEXP:%.*]], float [[TMP0:%.*]], i1 [[CMP:%.*]], float [[TMP1:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0x7FF8000000000000, float poison, float poison>, float [[TMP1]], i32 29; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[TMP0]], i32 310; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]11; CHECK: [[IF_THEN]]:12; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> poison, <2 x i32> <i32 3, i32 3>13; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x float> [[TMP5]], zeroinitializer14; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[NEXP]], align 415; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> [[TMP5]], float [[TMP4]], i32 016; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x float> [[TMP6]], zeroinitializer17; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float poison>, float [[TMP1]], i32 318; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP8]], <2 x float> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>19; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> [[TMP10]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>20; CHECK-NEXT: br label %[[IF_END]]21; CHECK: [[IF_END]]:22; CHECK-NEXT: [[TMP12:%.*]] = phi <4 x float> [ [[TMP11]], %[[IF_THEN]] ], [ [[TMP3]], %[[ENTRY]] ]23; CHECK-NEXT: [[TMP13:%.*]] = phi <2 x float> [ [[TMP8]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]24; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x float> [ zeroinitializer, %[[IF_THEN]] ], [ <float 0x7FF8000000000000, float 1.000000e+00>, %[[ENTRY]] ]25; CHECK-NEXT: [[TMP15:%.*]] = phi <2 x float> [ [[TMP7]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]26; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x float> [[TMP14]], <2 x float> <float poison, float 0.000000e+00>, <2 x i32> <i32 1, i32 3>27; CHECK-NEXT: [[TMP17:%.*]] = fmul <2 x float> [[TMP15]], [[TMP16]]28; CHECK-NEXT: [[TMP18:%.*]] = fmul <2 x float> [[TMP13]], [[TMP14]]29; CHECK-NEXT: [[TMP19:%.*]] = fmul <4 x float> [[TMP12]], zeroinitializer30; CHECK-NEXT: [[CALL25:%.*]] = load volatile ptr, ptr null, align 831; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x float> [[TMP18]], [[TMP17]]32; CHECK-NEXT: [[TMP21:%.*]] = fmul <2 x float> [[TMP20]], zeroinitializer33; CHECK-NEXT: [[TMP22:%.*]] = fadd <2 x float> [[TMP21]], zeroinitializer34; CHECK-NEXT: [[TMP23:%.*]] = fmul <4 x float> [[TMP19]], zeroinitializer35; CHECK-NEXT: [[TMP24:%.*]] = fadd <4 x float> [[TMP19]], zeroinitializer36; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x float> [[TMP23]], <4 x float> [[TMP24]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>37; CHECK-NEXT: [[TMP28:%.*]] = shufflevector <2 x float> [[TMP22]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>38; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <4 x float> <float 0.000000e+00, float 1.000000e+00, float poison, float poison>, <4 x float> [[TMP28]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>39; CHECK-NEXT: [[TMP27:%.*]] = fadd <4 x float> [[TMP25]], [[TMP26]]40; CHECK-NEXT: store <4 x float> [[TMP27]], ptr [[CALL25]], align 441; CHECK-NEXT: ret void42;43entry:44 br i1 %cmp, label %if.then, label %if.end45 46if.then:47 %div.i41 = fmul float %0, 0.000000e+0048 %2 = load float, ptr %nExp, align 449 %div.1.i.i = fmul float %2, 0.000000e+0050 %div.2.i.i = fmul float %0, 0.000000e+0051 br label %if.end52 53if.end:54 %3 = phi float [ %1, %if.then ], [ %0, %entry ]55 %4 = phi float [ 0.000000e+00, %if.then ], [ %1, %entry ]56 %5 = phi float [ 0.000000e+00, %if.then ], [ 0x7FF8000000000000, %entry ]57 %6 = phi float [ 0.000000e+00, %if.then ], [ 1.000000e+00, %entry ]58 %fa.sroa.9.0 = phi float [ %div.2.i.i, %if.then ], [ 0.000000e+00, %entry ]59 %fa.sroa.7.0 = phi float [ %div.1.i.i, %if.then ], [ 0.000000e+00, %entry ]60 %fa.sroa.0.0 = phi float [ %div.i41, %if.then ], [ 0.000000e+00, %entry ]61 %mul.1.i.i58 = fmul float %fa.sroa.7.0, %662 %mul.2.i.i60 = fmul float %fa.sroa.9.0, %663 %mul.1.i.i.i63 = fmul float %fa.sroa.0.0, %564 %mul.2.i.i.i65 = fmul float %fa.sroa.0.0, 0.000000e+0065 %mul.i66 = fmul float %fa.sroa.0.0, 0.000000e+0066 %add.1.i.i = fadd float %mul.1.i.i58, %mul.1.i.i.i6367 %add.2.i.i = fadd float %mul.2.i.i60, %mul.2.i.i.i6568 %mul.1.i.i74 = fmul float %add.1.i.i, 0.000000e+0069 %mul.2.i.i76 = fmul float %add.2.i.i, 0.000000e+0070 %mul.i.i.i78 = fmul float %mul.i66, 0.000000e+0071 %add.1.i.i85 = fadd float %mul.1.i.i74, 0.000000e+0072 %add.2.i.i86 = fadd float %mul.2.i.i76, 0.000000e+0073 %mul.i.i.i97 = fmul float %5, 0.000000e+0074 %mul.1.i.i.i99 = fmul float %4, 0.000000e+0075 %mul.2.i.i.i101 = fmul float %3, 0.000000e+0076 %add.i.i103 = fadd float %mul.i.i.i97, 0.000000e+0077 %add.1.i.i104 = fadd float %mul.1.i.i.i99, 0.000000e+0078 %add.2.i.i105 = fadd float %mul.2.i.i.i101, 0.000000e+0079 %add = fadd float %mul.i.i.i78, 0.000000e+0080 %add.i = fadd float %add.i.i103, 1.000000e+0081 %add.1.i = fadd float %add.1.i.i104, %add.1.i.i8582 %add.2.i = fadd float %add.2.i.i105, %add.2.i.i8683 %call25 = load volatile ptr, ptr null, align 884 store float %add, ptr %call25, align 485 %__trans_tmp_29.sroa.5.0.call25.sroa_idx = getelementptr i8, ptr %call25, i64 486 store float %add.i, ptr %__trans_tmp_29.sroa.5.0.call25.sroa_idx, align 487 %__trans_tmp_29.sroa.6.0.call25.sroa_idx = getelementptr i8, ptr %call25, i64 888 store float %add.1.i, ptr %__trans_tmp_29.sroa.6.0.call25.sroa_idx, align 489 %__trans_tmp_29.sroa.7.0.call25.sroa_idx = getelementptr i8, ptr %call25, i64 1290 store float %add.2.i, ptr %__trans_tmp_29.sroa.7.0.call25.sroa_idx, align 491 ret void92}93