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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-100 < %s | FileCheck %s3 4@f = global i32 zeroinitializer5 6define i32 @test() {7; CHECK-LABEL: define i32 @test() {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: store i32 152, ptr @f, align 410; CHECK-NEXT: [[AGG_TMP_SROA_0_0_COPYLOAD_I:%.*]] = load i32, ptr @f, align 411; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> <i32 poison, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080>, i32 [[AGG_TMP_SROA_0_0_COPYLOAD_I]], i32 012; CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i32> [[TMP3]], <i32 24, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>13; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> <i32 83886080, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[TMP0]]14; CHECK-NEXT: [[TMP2:%.*]] = ashr <8 x i32> [[TMP1]], splat (i32 24)15; CHECK-NEXT: [[TMP5:%.*]] = and <8 x i32> [[TMP2]], <i32 66440127, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>16; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> poison, <2 x i32> <i32 0, i32 poison>17; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 0, i32 3>18; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt <2 x i32> [[TMP7]], <i32 33554431, i32 0>19; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>20; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i1> <i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i1> [[TMP14]], <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>21; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP9]], <8 x i32> zeroinitializer, <8 x i32> <i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>22; CHECK-NEXT: [[TMP13:%.*]] = shl <8 x i32> [[TMP5]], [[TMP10]]23; CHECK-NEXT: [[TMP11:%.*]] = trunc <8 x i32> [[TMP13]] to <8 x i8>24; CHECK-NEXT: [[TMP12:%.*]] = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> [[TMP11]])25; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP12]] to i3226; CHECK-NEXT: ret i32 [[CONV]]27;28entry:29 store i32 152, ptr @f, align 430 %agg.tmp.sroa.0.0.copyload.i = load i32, ptr @f, align 431 %add.i.i = shl i32 %agg.tmp.sroa.0.0.copyload.i, 2432 %sext.i = add i32 %add.i.i, 8388608033 %conv2.i = ashr i32 %sext.i, 2434 %and.i = and i32 %conv2.i, 6644012735 %cmp3.i.i = icmp ugt i32 %and.i, 3355443136 %shl.i.i = select i1 %cmp3.i.i, i32 0, i32 637 %cond.i.i = shl i32 %and.i, %shl.i.i38 %0 = trunc i32 %cond.i.i to i839 %sext.1.i = add i32 0, 8388608040 %conv2.1.i = ashr i32 %sext.1.i, 2441 %and.1.i = and i32 %conv2.1.i, 142 %cmp3.i.1.i = icmp ugt i32 0, 043 %shl.i.1.i = select i1 %cmp3.i.1.i, i32 0, i32 044 %cond.i.1.i = shl i32 %and.1.i, %shl.i.1.i45 %1 = trunc i32 %cond.i.1.i to i846 %conv17.1.i = and i8 %0, %147 %sext.2.i = add i32 0, 8388608048 %conv2.2.i = ashr i32 %sext.2.i, 2449 %and.2.i = and i32 %conv2.2.i, 150 %shl.i.2.i = select i1 false, i32 0, i32 051 %cond.i.2.i = shl i32 %and.2.i, %shl.i.2.i52 %2 = trunc i32 %cond.i.2.i to i853 %conv17.2.i = and i8 %conv17.1.i, %254 %sext.3.i = add i32 0, 8388608055 %conv2.3.i = ashr i32 %sext.3.i, 2456 %and.3.i = and i32 %conv2.3.i, 157 %shl.i.3.i = select i1 false, i32 0, i32 058 %cond.i.3.i = shl i32 %and.3.i, %shl.i.3.i59 %3 = trunc i32 %cond.i.3.i to i860 %conv17.3.i = and i8 %conv17.2.i, %361 %sext.4.i = add i32 0, 8388608062 %conv2.4.i = ashr i32 %sext.4.i, 2463 %and.4.i = and i32 %conv2.4.i, 164 %shl.i.4.i = select i1 false, i32 0, i32 065 %cond.i.4.i = shl i32 %and.4.i, %shl.i.4.i66 %4 = trunc i32 %cond.i.4.i to i867 %conv17.4.i = and i8 %conv17.3.i, %468 %sext.5.i = add i32 0, 8388608069 %conv2.5.i = ashr i32 %sext.5.i, 2470 %and.5.i = and i32 %conv2.5.i, 171 %shl.i.5.i = select i1 false, i32 0, i32 072 %cond.i.5.i = shl i32 %and.5.i, %shl.i.5.i73 %5 = trunc i32 %cond.i.5.i to i874 %conv17.5.i = and i8 %conv17.4.i, %575 %sext.6.i = add i32 0, 8388608076 %conv2.6.i = ashr i32 %sext.6.i, 2477 %and.6.i = and i32 %conv2.6.i, 178 %shl.i.6.i = select i1 false, i32 0, i32 079 %cond.i.6.i = shl i32 %and.6.i, %shl.i.6.i80 %6 = trunc i32 %cond.i.6.i to i881 %conv17.6.i = and i8 %conv17.5.i, %682 %sext.7.i = add i32 0, 8388608083 %conv2.7.i = ashr i32 %sext.7.i, 2484 %and.7.i = and i32 %conv2.7.i, 185 %shl.i.7.i = select i1 false, i32 0, i32 086 %cond.i.7.i = shl i32 %and.7.i, %shl.i.7.i87 %7 = trunc i32 %cond.i.7.i to i888 %conv17.7.i = and i8 %conv17.6.i, %789 %conv = zext i8 %conv17.7.i to i3290 ret i32 %conv91}92 93