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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s3 4define i32 @test() {5; CHECK-LABEL: define i32 @test() {6; CHECK-NEXT: [[ENTRY:.*:]]7; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr null, align 168; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP0]], i32 19; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP12]], 010; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison>11; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>12; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> [[TMP3]], <8 x i64> <i64 poison, i64 poison, i64 poison, i64 poison, i64 0, i64 poison, i64 poison, i64 poison>, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 1, i32 poison, i32 poison>13; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> [[TMP3]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 poison, i32 poison>14; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i64> [[TMP5]] to <8 x i32>15; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5>16; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <8 x i32> <i32 1, i32 2, i32 2, i32 3, i32 3, i32 3, i32 2, i32 1>17; CHECK-NEXT: [[TMP14:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>18; CHECK-NEXT: [[TMP15:%.*]] = add <8 x i32> [[TMP14]], zeroinitializer19; CHECK-NEXT: [[TMP8:%.*]] = add <16 x i32> [[TMP7]], zeroinitializer20; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[TMP0]], i32 021; CHECK-NEXT: [[INC_3_3_I_1:%.*]] = or i64 [[TMP9]], 022; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x i32> [[TMP8]], <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>23; CHECK-NEXT: [[RDX_OP:%.*]] = or <8 x i32> [[TMP16]], [[TMP15]]24; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <8 x i32> [[RDX_OP]], <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>25; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <16 x i32> [[TMP8]], <16 x i32> [[TMP18]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>26; CHECK-NEXT: [[OP_RDX:%.*]] = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> [[TMP17]])27; CHECK-NEXT: ret i32 [[OP_RDX]]28;29entry:30 %.pre.i = load i64, ptr getelementptr inbounds nuw (i8, ptr null, i64 24), align 831 %.pre50.i = load i64, ptr getelementptr inbounds nuw (i8, ptr null, i64 16), align 1632 %.pre51.i = load i64, ptr getelementptr inbounds nuw (i8, ptr null, i64 8), align 833 %.pre52.i = load i64, ptr null, align 1634 %0 = or i64 %.pre51.i, 035 %1 = trunc i64 %.pre.i to i3236 %2 = add i32 %1, 037 %3 = trunc i64 %.pre50.i to i3238 %4 = add i32 %3, 039 %5 = trunc i64 %.pre51.i to i3240 %6 = add i32 %5, 041 %7 = trunc i64 0 to i3242 %8 = add i32 %5, 043 %9 = add i32 %7, 044 %10 = add i32 %1, 045 %11 = add i32 %3, 046 %12 = add i32 %5, 047 %13 = add i32 %7, 048 %14 = trunc i64 %.pre.i to i3249 %15 = add i32 %14, 050 %16 = trunc i64 %.pre50.i to i3251 %17 = add i32 %16, 052 %18 = trunc i64 %.pre51.i to i3253 %19 = add i32 %18, 054 %20 = trunc i64 %.pre52.i to i3255 %conv14.1.i = or i32 %9, %1356 %21 = or i32 %conv14.1.i, %657 %22 = or i32 %21, %858 %23 = or i32 %22, %1259 %24 = or i32 %23, %460 %25 = or i32 %24, %1161 %26 = or i32 %25, %262 %27 = or i32 %26, %1063 %28 = or i32 %27, %1564 %29 = or i32 %28, %1765 %30 = or i32 %29, %1966 %31 = add i32 %14, 067 %32 = add i32 %16, 068 %33 = add i32 %18, 069 %34 = add i32 %20, 070 %35 = add i32 %14, 071 %36 = add i32 %16, 072 %37 = add i32 %18, 073 %38 = add i32 %20, 074 %39 = add i32 %14, 075 %40 = add i32 %16, 076 %41 = add i32 %18, 077 %42 = add i32 %20, 078 %inc.3.3.i.1 = or i64 %.pre52.i, 079 %conv14.i.1 = or i32 %38, %3480 %conv14.1.i.1 = or i32 %conv14.i.1, %4281 %conv14.3.i.1 = or i32 %conv14.1.i.1, %3382 %conv14.145.i.1 = or i32 %conv14.3.i.1, %3783 %conv14.1.1.i.1 = or i32 %conv14.145.i.1, %4184 %conv14.3.1.i.1 = or i32 %conv14.1.1.i.1, %3285 %conv14.247.i.1 = or i32 %conv14.3.1.i.1, %3686 %conv14.1.2.i.1 = or i32 %conv14.247.i.1, %4087 %conv14.3.2.i.1 = or i32 %conv14.1.2.i.1, %3188 %conv14.349.i.1 = or i32 %conv14.3.2.i.1, %3589 %conv14.1.3.i.1 = or i32 %conv14.349.i.1, %3990 %conv14.3.3.i.1 = or i32 %conv14.1.3.i.1, %3091 ret i32 %conv14.3.3.i.192}93