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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-apple-macosx -mcpu=haswell | FileCheck %s --check-prefixes=CHECK,AVX23; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-apple-macosx -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX5124 5;unsigned load_le32(unsigned char *data) {6; unsigned le32 = (data[0]<<0) | (data[1]<<8) | (data[2]<<16) | (data[3]<<24);7; return le32;8;}9 10define i32 @_Z9load_le32Ph(ptr nocapture readonly %data) {11; CHECK-LABEL: @_Z9load_le32Ph(12; CHECK-NEXT: entry:13; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 114; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i3215; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 116; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 117; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i3218; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 819; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL3]], [[CONV]]20; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 221; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 122; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i3223; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 1624; CHECK-NEXT: [[OR7:%.*]] = or i32 [[OR]], [[SHL6]]25; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 326; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 127; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i3228; CHECK-NEXT: [[SHL10:%.*]] = shl nuw i32 [[CONV9]], 2429; CHECK-NEXT: [[OR11:%.*]] = or i32 [[OR7]], [[SHL10]]30; CHECK-NEXT: ret i32 [[OR11]]31;32entry:33 %0 = load i8, ptr %data, align 134 %conv = zext i8 %0 to i3235 %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 136 %1 = load i8, ptr %arrayidx1, align 137 %conv2 = zext i8 %1 to i3238 %shl3 = shl nuw nsw i32 %conv2, 839 %or = or i32 %shl3, %conv40 %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 241 %2 = load i8, ptr %arrayidx4, align 142 %conv5 = zext i8 %2 to i3243 %shl6 = shl nuw nsw i32 %conv5, 1644 %or7 = or i32 %or, %shl645 %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 346 %3 = load i8, ptr %arrayidx8, align 147 %conv9 = zext i8 %3 to i3248 %shl10 = shl nuw i32 %conv9, 2449 %or11 = or i32 %or7, %shl1050 ret i32 %or1151}52 53define <4 x float> @PR16739_byref(ptr nocapture readonly dereferenceable(16) %x) {54; AVX2-LABEL: @PR16739_byref(55; AVX2-NEXT: [[GEP2:%.*]] = getelementptr inbounds <4 x float>, ptr [[X:%.*]], i64 0, i64 256; AVX2-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[X]], align 457; AVX2-NEXT: [[X2:%.*]] = load float, ptr [[GEP2]], align 458; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>59; AVX2-NEXT: [[I2:%.*]] = insertelement <4 x float> [[TMP2]], float [[X2]], i32 260; AVX2-NEXT: [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[X2]], i32 361; AVX2-NEXT: ret <4 x float> [[I3]]62;63; AVX512-LABEL: @PR16739_byref(64; AVX512-NEXT: [[GEP1:%.*]] = getelementptr inbounds <4 x float>, ptr [[X:%.*]], i64 0, i64 165; AVX512-NEXT: [[X0:%.*]] = load float, ptr [[X]], align 466; AVX512-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[GEP1]], align 467; AVX512-NEXT: [[I0:%.*]] = insertelement <4 x float> undef, float [[X0]], i32 068; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>69; AVX512-NEXT: [[I21:%.*]] = shufflevector <4 x float> [[I0]], <4 x float> [[TMP2]], <4 x i32> <i32 0, i32 4, i32 5, i32 3>70; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[I21]], <4 x float> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>71; AVX512-NEXT: ret <4 x float> [[TMP3]]72;73 %gep1 = getelementptr inbounds <4 x float>, ptr %x, i64 0, i64 174 %gep2 = getelementptr inbounds <4 x float>, ptr %x, i64 0, i64 275 %x0 = load float, ptr %x76 %x1 = load float, ptr %gep177 %x2 = load float, ptr %gep278 %i0 = insertelement <4 x float> undef, float %x0, i32 079 %i1 = insertelement <4 x float> %i0, float %x1, i32 180 %i2 = insertelement <4 x float> %i1, float %x2, i32 281 %i3 = insertelement <4 x float> %i2, float %x2, i32 382 ret <4 x float> %i383}84 85define <4 x float> @PR16739_byref_alt(ptr nocapture readonly dereferenceable(16) %x) {86; CHECK-LABEL: @PR16739_byref_alt(87; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[X:%.*]], align 488; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>89; CHECK-NEXT: ret <4 x float> [[TMP2]]90;91 %gep1 = getelementptr inbounds <4 x float>, ptr %x, i64 0, i64 192 %x0 = load float, ptr %x93 %x1 = load float, ptr %gep194 %i0 = insertelement <4 x float> undef, float %x0, i32 095 %i1 = insertelement <4 x float> %i0, float %x0, i32 196 %i2 = insertelement <4 x float> %i1, float %x1, i32 297 %i3 = insertelement <4 x float> %i2, float %x1, i32 398 ret <4 x float> %i399}100 101define <4 x float> @PR16739_byval(ptr nocapture readonly dereferenceable(16) %x) {102; CHECK-LABEL: @PR16739_byval(103; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[X:%.*]], align 16104; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>105; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i64> [[TMP2]], <i64 0, i64 32, i64 0, i64 0>106; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i32>107; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>108; CHECK-NEXT: ret <4 x float> [[TMP5]]109;110 %t1 = load i64, ptr %x, align 16111 %t2 = getelementptr inbounds <4 x float>, ptr %x, i64 0, i64 2112 %t4 = load i64, ptr %t2, align 8113 %t5 = trunc i64 %t1 to i32114 %t6 = bitcast i32 %t5 to float115 %t7 = insertelement <4 x float> undef, float %t6, i32 0116 %t8 = lshr i64 %t1, 32117 %t9 = trunc i64 %t8 to i32118 %t10 = bitcast i32 %t9 to float119 %t11 = insertelement <4 x float> %t7, float %t10, i32 1120 %t12 = trunc i64 %t4 to i32121 %t13 = bitcast i32 %t12 to float122 %t14 = insertelement <4 x float> %t11, float %t13, i32 2123 %t15 = insertelement <4 x float> %t14, float %t13, i32 3124 ret <4 x float> %t15125}126 127define void @PR43578_prefer128(ptr %r, ptr %p, ptr %q) #0 {128; CHECK-LABEL: @PR43578_prefer128(129; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i64, ptr [[P:%.*]], i64 2130; CHECK-NEXT: [[Q2:%.*]] = getelementptr inbounds i64, ptr [[Q:%.*]], i64 2131; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[P]], align 2132; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[Q]], align 2133; CHECK-NEXT: [[TMP3:%.*]] = sub nsw <2 x i64> [[TMP1]], [[TMP2]]134; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[P2]], align 2135; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr [[Q2]], align 2136; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <2 x i64> [[TMP4]], [[TMP5]]137; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0138; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[R:%.*]], i64 [[TMP7]]139; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1140; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP8]]141; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i32 0142; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP9]]143; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP6]], i32 1144; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP10]]145; CHECK-NEXT: ret void146;147 %p1 = getelementptr inbounds i64, ptr %p, i64 1148 %p2 = getelementptr inbounds i64, ptr %p, i64 2149 %p3 = getelementptr inbounds i64, ptr %p, i64 3150 151 %q1 = getelementptr inbounds i64, ptr %q, i64 1152 %q2 = getelementptr inbounds i64, ptr %q, i64 2153 %q3 = getelementptr inbounds i64, ptr %q, i64 3154 155 %x0 = load i64, ptr %p, align 2156 %x1 = load i64, ptr %p1, align 2157 %x2 = load i64, ptr %p2, align 2158 %x3 = load i64, ptr %p3, align 2159 160 %y0 = load i64, ptr %q, align 2161 %y1 = load i64, ptr %q1, align 2162 %y2 = load i64, ptr %q2, align 2163 %y3 = load i64, ptr %q3, align 2164 165 %sub0 = sub nsw i64 %x0, %y0166 %sub1 = sub nsw i64 %x1, %y1167 %sub2 = sub nsw i64 %x2, %y2168 %sub3 = sub nsw i64 %x3, %y3169 170 %g0 = getelementptr inbounds i32, ptr %r, i64 %sub0171 %g1 = getelementptr inbounds i32, ptr %r, i64 %sub1172 %g2 = getelementptr inbounds i32, ptr %r, i64 %sub2173 %g3 = getelementptr inbounds i32, ptr %r, i64 %sub3174 ret void175}176 177attributes #0 = { "prefer-vector-width"="128" }178