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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"5target triple = "x86_64-unknown-linux-gnu"6 7; Make sure we do not generate malformed phis not in the beginning of block.8define void @test() #0 {9; CHECK-LABEL: @test(10; CHECK-NEXT: bb:11; CHECK-NEXT: br label [[BB1:%.*]]12; CHECK: bb1:13; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 1, [[BB1]] ], [ 2, [[BB:%.*]] ]14; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[TMP18:%.*]], [[BB1]] ], [ 3, [[BB]] ]15; CHECK-NEXT: [[TMP3:%.*]] = mul i32 4, [[TMP]]16; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP]]17; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP]]18; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP]]19; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[TMP6]], [[TMP]]20; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP]]21; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], [[TMP]]22; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP]]23; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP]]24; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP]]25; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP]]26; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP]]27; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP]]28; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP]]29; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], [[TMP]]30; CHECK-NEXT: [[TMP18]] = mul i32 [[TMP17]], [[TMP]]31; CHECK-NEXT: br label [[BB1]]32;33bb:34 br label %bb135 36bb1: ; preds = %bb1, %bb37 %tmp = phi i32 [ 1, %bb1 ], [ 2, %bb ]38 %tmp2 = phi i32 [ %tmp18, %bb1 ], [ 3, %bb ]39 %tmp3 = mul i32 4, %tmp40 %tmp4 = mul i32 %tmp3, %tmp41 %tmp5 = mul i32 %tmp4, %tmp42 %tmp6 = mul i32 %tmp5, %tmp43 %tmp7 = mul i32 %tmp6, %tmp44 %tmp8 = mul i32 %tmp7, %tmp45 %tmp9 = mul i32 %tmp8, %tmp46 %tmp10 = mul i32 %tmp9, %tmp47 %tmp11 = mul i32 %tmp10, %tmp48 %tmp12 = mul i32 %tmp11, %tmp49 %tmp13 = mul i32 %tmp12, %tmp50 %tmp14 = mul i32 %tmp13, %tmp51 %tmp15 = mul i32 %tmp14, %tmp52 %tmp16 = mul i32 %tmp15, %tmp53 %tmp17 = mul i32 %tmp16, %tmp54 %tmp18 = mul i32 %tmp17, %tmp55 br label %bb156}57 58define void @test_2(ptr addrspace(1) %arg, i32 %arg1) #0 {59; CHECK-LABEL: @test_2(60; CHECK-NEXT: bb:61; CHECK-NEXT: br label [[BB2:%.*]]62; CHECK: bb2:63; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 3, [[BB:%.*]] ], [ 3, [[BB2]] ]64; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ 0, [[BB]] ], [ 3, [[BB2]] ]65; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[TMP]], 866; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 27, [[TMP0]]67; CHECK-NEXT: call void @use(i32 [[OP_RDX]])68; CHECK-NEXT: br label [[BB2]]69;70bb:71 br label %bb272 73bb2: ; preds = %bb2, %bb74 %tmp = phi i32 [ 3, %bb ], [ 3, %bb2 ]75 %tmp3 = phi i32 [ 0, %bb ], [ 3, %bb2 ]76 %tmp4 = add i32 %tmp, 377 %tmp5 = add i32 3, %tmp478 %tmp6 = add i32 %tmp, %tmp579 %tmp7 = add i32 3, %tmp680 %tmp8 = add i32 %tmp, %tmp781 %tmp9 = add i32 3, %tmp882 %tmp10 = add i32 %tmp, %tmp983 %tmp11 = add i32 3, %tmp1084 %tmp12 = add i32 %tmp, %tmp1185 %tmp13 = add i32 3, %tmp1286 %tmp14 = add i32 %tmp, %tmp1387 %tmp15 = add i32 3, %tmp1488 %tmp16 = add i32 %tmp, %tmp1589 %tmp17 = add i32 3, %tmp1690 %tmp18 = add i32 %tmp, %tmp1791 %tmp19 = add i32 3, %tmp1892 call void @use(i32 %tmp19)93 br label %bb294}95 96; Make sure we don't crash.97define i64 @test_3() #0 {98; CHECK-LABEL: @test_3(99; CHECK-NEXT: bb:100; CHECK-NEXT: br label [[BB1:%.*]]101; CHECK: bb1:102; CHECK-NEXT: br label [[BB3:%.*]]103; CHECK: bb2:104; CHECK-NEXT: br label [[BB3]]105; CHECK: bb3:106; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x i32> [ splat (i32 3), [[BB1]] ], [ poison, [[BB2:%.*]] ]107; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <28 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1>108; CHECK-NEXT: [[VAL4:%.*]] = extractelement <28 x i32> [[TMP3]], i32 0109; CHECK-NEXT: [[TMP0:%.*]] = insertelement <32 x i32> poison, i32 [[VAL4]], i32 0110; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> [[TMP0]], <32 x i32> poison, <32 x i32> zeroinitializer111; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> [[TMP1]], <32 x i32> poison, <28 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>112; CHECK-NEXT: [[RDX_OP:%.*]] = mul <28 x i32> [[TMP5]], [[TMP3]]113; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <28 x i32> [[RDX_OP]], <28 x i32> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 poison, i32 poison, i32 poison, i32 poison>114; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <32 x i32> [[TMP1]], <32 x i32> [[TMP7]], <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 28, i32 29, i32 30, i32 31>115; CHECK-NEXT: [[OP_RDX27:%.*]] = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> [[TMP6]])116; CHECK-NEXT: [[VAL64:%.*]] = add i32 3, [[OP_RDX27]]117; CHECK-NEXT: [[VAL65:%.*]] = sext i32 [[VAL64]] to i64118; CHECK-NEXT: ret i64 [[VAL65]]119;120bb:121 br label %bb1122 123bb1: ; preds = %bb124 br label %bb3125 126bb2: ; No predecessors!127 br label %bb3128 129bb3: ; preds = %bb2, %bb1130 %val = phi i32 [ 3, %bb1 ], [ 3, %bb2 ]131 %val4 = phi i32 [ 3, %bb1 ], [ 3, %bb2 ]132 %val5 = mul i32 %val, %val4133 %val6 = mul i32 %val5, %val4134 %val7 = mul i32 %val6, %val4135 %val8 = mul i32 %val7, %val4136 %val9 = mul i32 %val8, %val4137 %val10 = mul i32 %val9, %val4138 %val11 = mul i32 %val10, %val4139 %val12 = mul i32 %val11, %val4140 %val13 = mul i32 %val12, %val4141 %val14 = mul i32 %val13, %val4142 %val15 = mul i32 %val14, %val4143 %val16 = mul i32 %val15, %val4144 %val17 = mul i32 %val16, %val4145 %val18 = mul i32 %val17, %val4146 %val19 = mul i32 %val18, %val4147 %val20 = mul i32 %val19, %val4148 %val21 = mul i32 %val20, %val4149 %val22 = mul i32 %val21, %val4150 %val23 = mul i32 %val22, %val4151 %val24 = mul i32 %val23, %val4152 %val25 = mul i32 %val24, %val4153 %val26 = mul i32 %val25, %val4154 %val27 = mul i32 %val26, %val4155 %val28 = mul i32 %val27, %val4156 %val29 = mul i32 %val28, %val4157 %val30 = mul i32 %val29, %val4158 %val31 = mul i32 %val30, %val4159 %val32 = mul i32 %val31, %val4160 %val33 = mul i32 %val32, %val4161 %val34 = mul i32 %val33, %val4162 %val35 = mul i32 %val34, %val4163 %val36 = mul i32 %val35, %val4164 %val37 = mul i32 %val36, %val4165 %val38 = mul i32 %val37, %val4166 %val39 = mul i32 %val38, %val4167 %val40 = mul i32 %val39, %val4168 %val41 = mul i32 %val40, %val4169 %val42 = mul i32 %val41, %val4170 %val43 = mul i32 %val42, %val4171 %val44 = mul i32 %val43, %val4172 %val45 = mul i32 %val44, %val4173 %val46 = mul i32 %val45, %val4174 %val47 = mul i32 %val46, %val4175 %val48 = mul i32 %val47, %val4176 %val49 = mul i32 %val48, %val4177 %val50 = mul i32 %val49, %val4178 %val51 = mul i32 %val50, %val4179 %val52 = mul i32 %val51, %val4180 %val53 = mul i32 %val52, %val4181 %val54 = mul i32 %val53, %val4182 %val55 = mul i32 %val54, %val4183 %val56 = mul i32 %val55, %val4184 %val57 = mul i32 %val56, %val4185 %val58 = mul i32 %val57, %val4186 %val59 = mul i32 %val58, %val4187 %val60 = mul i32 %val59, %val4188 %val61 = mul i32 %val60, %val4189 %val62 = mul i32 %val61, %val4190 %val63 = mul i32 %val62, %val4191 %val64 = add i32 3, %val63192 %val65 = sext i32 %val64 to i64193 ret i64 %val65194}195 196declare void @use(i32) #0197 198attributes #0 = { "target-features"="+sse4.1" }199