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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -slp-threshold=-6 -passes=slp-vectorizer -mattr=+sse2 -S | FileCheck %s --check-prefix=SSE3; RUN: opt < %s -slp-threshold=-6 -passes=slp-vectorizer -mattr=+avx -S | FileCheck %s --check-prefix=AVX4; RUN: opt < %s -slp-threshold=-6 -passes=slp-vectorizer -mattr=+avx2 -S | FileCheck %s --check-prefix=AVX5; RUN: opt < %s -slp-threshold=-6 -passes=slp-vectorizer -mattr=+avx512f -S | FileCheck %s --check-prefix=AVX6; RUN: opt < %s -slp-threshold=-6 -passes=slp-vectorizer -mattr=+avx512vl -S | FileCheck %s --check-prefix=AVX7 8target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"9target triple = "x86_64-unknown-linux-gnu"10 11; These tests ensure that we do not regress due to PR31243. Note that we set12; the SLP threshold to force vectorization even when not profitable.13 14; When computing minimum sizes, if we can prove the sign bit is zero, we can15; zero-extend the roots back to their original sizes.16;17define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {18; SSE-LABEL: @PR31243_zext(19; SSE-NEXT: entry:20; SSE-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 021; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 122; SSE-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)23; SSE-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 024; SSE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i3225; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]26; SSE-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 127; SSE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3228; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]29; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 130; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 131; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]32; SSE-NEXT: ret i8 [[T8]]33;34; AVX-LABEL: @PR31243_zext(35; AVX-NEXT: entry:36; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 037; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 138; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)39; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 040; AVX-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i3241; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]42; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 143; AVX-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3244; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]45; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 146; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 147; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]48; AVX-NEXT: ret i8 [[T8]]49;50entry:51 %t0 = zext i8 %v0 to i3252 %t1 = zext i8 %v1 to i3253 %t2 = or i32 %t0, 154 %t3 = or i32 %t1, 155 %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t256 %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t357 %t6 = load i8, ptr %t458 %t7 = load i8, ptr %t559 %t8 = add i8 %t6, %t760 ret i8 %t861}62 63; When computing minimum sizes, if we cannot prove the sign bit is zero, we64; have to include one extra bit for signedness since we will sign-extend the65; roots.66;67; FIXME: This test is suboptimal since the compuation can be performed in i8.68; In general, we need to add an extra bit to the maximum bit width only69; if we can't prove that the upper bit of the original type is equal to70; the upper bit of the proposed smaller type. If these two bits are the71; same (either zero or one) we know that sign-extending from the smaller72; type will result in the same value. Since we don't yet perform this73; optimization, we make the proposed smaller type (i8) larger (i16) to74; ensure correctness.75;76define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {77; SSE-LABEL: @PR31243_sext(78; SSE-NEXT: entry:79; SSE-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 080; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 181; SSE-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)82; SSE-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 083; SSE-NEXT: [[TMP4:%.*]] = sext i8 [[TMP3]] to i3284; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]85; SSE-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 186; SSE-NEXT: [[TMP6:%.*]] = sext i8 [[TMP5]] to i3287; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]88; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 189; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 190; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]91; SSE-NEXT: ret i8 [[T8]]92;93; AVX-LABEL: @PR31243_sext(94; AVX-NEXT: entry:95; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 096; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 197; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)98; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 099; AVX-NEXT: [[TMP4:%.*]] = sext i8 [[TMP3]] to i32100; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]101; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1102; AVX-NEXT: [[TMP6:%.*]] = sext i8 [[TMP5]] to i32103; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]104; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1105; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1106; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]107; AVX-NEXT: ret i8 [[T8]]108;109entry:110 %t0 = sext i8 %v0 to i32111 %t1 = sext i8 %v1 to i32112 %t2 = or i32 %t0, 1113 %t3 = or i32 %t1, 1114 %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t2115 %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t3116 %t6 = load i8, ptr %t4117 %t7 = load i8, ptr %t5118 %t8 = add i8 %t6, %t7119 ret i8 %t8120}121