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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=znver2 < %s | FileCheck %s3 4define void @foo(ptr %arg) {5; CHECK-LABEL: define void @foo(6; CHECK-SAME: ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[BB:.*]]:8; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr null(i32 9, i64 16, i64 816, i64 400, i64 0)9; CHECK-NEXT: [[ICMP:%.*]] = icmp eq ptr [[CALL]], null10; CHECK-NEXT: [[ADD:%.*]] = add <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, splat (i16 16)11; CHECK-NEXT: [[AND:%.*]] = and <16 x i64> zeroinitializer, splat (i64 1)12; CHECK-NEXT: [[ADD1:%.*]] = add nuw nsw i64 0, 4813; CHECK-NEXT: [[SELECT:%.*]] = select <16 x i1> zeroinitializer, <16 x i16> zeroinitializer, <16 x i16> zeroinitializer14; CHECK-NEXT: [[ADD2:%.*]] = add nsw <16 x i16> [[SELECT]], splat (i16 -6124)15; CHECK-NEXT: [[ADD3:%.*]] = add <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, splat (i16 64)16; CHECK-NEXT: [[SUB:%.*]] = sub nsw <16 x i16> zeroinitializer, [[ADD3]]17; CHECK-NEXT: [[SELECT4:%.*]] = select <16 x i1> zeroinitializer, <16 x i16> [[ADD3]], <16 x i16> [[SUB]]18; CHECK-NEXT: [[ADD5:%.*]] = add <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>, splat (i64 80)19; CHECK-NEXT: [[FADD:%.*]] = fadd float 0.000000e+00, -1.580000e+0220; CHECK-NEXT: store float 0.000000e+00, ptr null, align 421; CHECK-NEXT: [[ICMP6:%.*]] = icmp eq i32 0, 022; CHECK-NEXT: call void null()23; CHECK-NEXT: [[MUL:%.*]] = mul i32 0, 924; CHECK-NEXT: br label %[[BB7:.*]]25; CHECK: [[BB7]]:26; CHECK-NEXT: [[PHI:%.*]] = phi float [ 4.000000e+00, %[[BB]] ], [ 0.000000e+00, %[[BB27:.*]] ]27; CHECK-NEXT: [[FADD8:%.*]] = fadd float 0.000000e+00, 0.000000e+0028; CHECK-NEXT: [[FADD9:%.*]] = fadd float [[PHI]], 1.000000e+0029; CHECK-NEXT: [[TMP2:%.*]] = fadd float [[FADD9]], 1.000000e+0030; CHECK-NEXT: [[FADD11:%.*]] = fadd float 0.000000e+00, 0.000000e+0031; CHECK-NEXT: [[FREM:%.*]] = frem float [[TMP2]], 7.000000e+0032; CHECK-NEXT: [[CALL12:%.*]] = call i32 @llvm.x86.sse.cvttss2si(<4 x float> zeroinitializer)33; CHECK-NEXT: switch i32 [[CALL12]], label %[[BB13:.*]] [34; CHECK-NEXT: i32 125, label %[[BB30:.*]]35; CHECK-NEXT: i32 98, label %[[BB30]]36; CHECK-NEXT: i32 99, label %[[BB30]]37; CHECK-NEXT: i32 103, label %[[BB30]]38; CHECK-NEXT: i32 112, label %[[BB30]]39; CHECK-NEXT: i32 116, label %[[BB30]]40; CHECK-NEXT: i32 121, label %[[BB30]]41; CHECK-NEXT: ]42; CHECK: [[BB13]]:43; CHECK-NEXT: [[FMUL:%.*]] = fmul double 0.000000e+00, 1.220000e+0244; CHECK-NEXT: [[MUL14:%.*]] = mul i32 0, -345; CHECK-NEXT: [[MUL15:%.*]] = mul i32 [[MUL14]], -346; CHECK-NEXT: [[CALL16:%.*]] = call i32 @llvm.x86.sse.cvttss2si(<4 x float> zeroinitializer)47; CHECK-NEXT: switch i32 [[CALL16]], label %[[BB17:.*]] [48; CHECK-NEXT: i32 125, label %[[BB30]]49; CHECK-NEXT: i32 98, label %[[BB30]]50; CHECK-NEXT: i32 99, label %[[BB30]]51; CHECK-NEXT: i32 103, label %[[BB30]]52; CHECK-NEXT: i32 112, label %[[BB30]]53; CHECK-NEXT: i32 116, label %[[BB30]]54; CHECK-NEXT: i32 121, label %[[BB30]]55; CHECK-NEXT: ]56; CHECK: [[BB17]]:57; CHECK-NEXT: [[FADD18:%.*]] = fadd float 0.000000e+00, 1.000000e+0058; CHECK-NEXT: [[MUL19:%.*]] = mul i32 [[MUL15]], -359; CHECK-NEXT: br label %[[BB20:.*]]60; CHECK: [[BB20]]:61; CHECK-NEXT: [[FADD21:%.*]] = fadd float [[FADD18]], 1.000000e+0062; CHECK-NEXT: switch i32 0, label %[[BB22:.*]] [63; CHECK-NEXT: i32 125, label %[[BB30]]64; CHECK-NEXT: i32 98, label %[[BB30]]65; CHECK-NEXT: i32 99, label %[[BB30]]66; CHECK-NEXT: i32 103, label %[[BB30]]67; CHECK-NEXT: i32 112, label %[[BB30]]68; CHECK-NEXT: i32 116, label %[[BB30]]69; CHECK-NEXT: i32 121, label %[[BB30]]70; CHECK-NEXT: ]71; CHECK: [[BB22]]:72; CHECK-NEXT: [[TMP5:%.*]] = fadd float [[FADD21]], 1.000000e+0073; CHECK-NEXT: [[TMP6:%.*]] = fadd float 0.000000e+00, 0.000000e+0074; CHECK-NEXT: [[FREM25:%.*]] = frem float [[TMP5]], 7.000000e+0075; CHECK-NEXT: [[FMUL26:%.*]] = fmul float [[FREM25]], 5.000000e+0076; CHECK-NEXT: switch i32 0, label %[[BB27]] [77; CHECK-NEXT: i32 125, label %[[BB30]]78; CHECK-NEXT: i32 98, label %[[BB30]]79; CHECK-NEXT: i32 99, label %[[BB30]]80; CHECK-NEXT: i32 103, label %[[BB30]]81; CHECK-NEXT: i32 112, label %[[BB30]]82; CHECK-NEXT: i32 116, label %[[BB30]]83; CHECK-NEXT: i32 121, label %[[BB30]]84; CHECK-NEXT: ]85; CHECK: [[BB27]]:86; CHECK-NEXT: [[FADD28:%.*]] = fadd float [[TMP5]], 1.000000e+0087; CHECK-NEXT: [[FADD29:%.*]] = fadd float [[TMP6]], 0.000000e+0088; CHECK-NEXT: br label %[[BB7]]89; CHECK: [[BB30]]:90; CHECK-NEXT: [[PHI31:%.*]] = phi float [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ [[TMP2]], %[[BB7]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[FADD21]], %[[BB20]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ], [ [[TMP5]], %[[BB22]] ]91; CHECK-NEXT: [[PHI32:%.*]] = phi float [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ [[FADD11]], %[[BB7]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB13]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ 0.000000e+00, %[[BB20]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ], [ [[TMP6]], %[[BB22]] ]92; CHECK-NEXT: ret void93;94bb:95 %call = call noalias ptr null(i32 9, i64 16, i64 816, i64 400, i64 0)96 %icmp = icmp eq ptr %call, null97 %add = add <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, splat (i16 16)98 %and = and <16 x i64> zeroinitializer, splat (i64 1)99 %add1 = add nuw nsw i64 0, 48100 %select = select <16 x i1> zeroinitializer, <16 x i16> zeroinitializer, <16 x i16> zeroinitializer101 %add2 = add nsw <16 x i16> %select, splat (i16 -6124)102 %add3 = add <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, splat (i16 64)103 %sub = sub nsw <16 x i16> zeroinitializer, %add3104 %select4 = select <16 x i1> zeroinitializer, <16 x i16> %add3, <16 x i16> %sub105 %add5 = add <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>, splat (i64 80)106 %fadd = fadd float 0.000000e+00, -1.580000e+02107 store float 0.000000e+00, ptr null, align 4108 %icmp6 = icmp eq i32 0, 0109 call void null()110 %mul = mul i32 0, 9111 br label %bb7112 113bb7:114 %phi = phi float [ 4.000000e+00, %bb ], [ 0.000000e+00, %bb27 ]115 %fadd8 = fadd float 0.000000e+00, 0.000000e+00116 %fadd9 = fadd float %phi, 1.000000e+00117 %fadd10 = fadd float %fadd9, 1.000000e+00118 %fadd11 = fadd float 0.000000e+00, 0.000000e+00119 %frem = frem float %fadd10, 7.000000e+00120 %call12 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> zeroinitializer)121 switch i32 %call12, label %bb13 [122 i32 125, label %bb30123 i32 98, label %bb30124 i32 99, label %bb30125 i32 103, label %bb30126 i32 112, label %bb30127 i32 116, label %bb30128 i32 121, label %bb30129 ]130 131bb13:132 %fmul = fmul double 0.000000e+00, 1.220000e+02133 %mul14 = mul i32 0, -3134 %mul15 = mul i32 %mul14, -3135 %call16 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> zeroinitializer)136 switch i32 %call16, label %bb17 [137 i32 125, label %bb30138 i32 98, label %bb30139 i32 99, label %bb30140 i32 103, label %bb30141 i32 112, label %bb30142 i32 116, label %bb30143 i32 121, label %bb30144 ]145 146bb17:147 %fadd18 = fadd float 0.000000e+00, 1.000000e+00148 %mul19 = mul i32 %mul15, -3149 br label %bb20150 151bb20:152 %fadd21 = fadd float %fadd18, 1.000000e+00153 switch i32 0, label %bb22 [154 i32 125, label %bb30155 i32 98, label %bb30156 i32 99, label %bb30157 i32 103, label %bb30158 i32 112, label %bb30159 i32 116, label %bb30160 i32 121, label %bb30161 ]162 163bb22:164 %fadd23 = fadd float %fadd21, 1.000000e+00165 %fadd24 = fadd float 0.000000e+00, 0.000000e+00166 %frem25 = frem float %fadd23, 7.000000e+00167 %fmul26 = fmul float %frem25, 5.000000e+00168 switch i32 0, label %bb27 [169 i32 125, label %bb30170 i32 98, label %bb30171 i32 99, label %bb30172 i32 103, label %bb30173 i32 112, label %bb30174 i32 116, label %bb30175 i32 121, label %bb30176 ]177 178bb27:179 %fadd28 = fadd float %fadd23, 1.000000e+00180 %fadd29 = fadd float %fadd24, 0.000000e+00181 br label %bb7182 183bb30:184 %phi31 = phi float [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ %fadd10, %bb7 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd21, %bb20 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ], [ %fadd23, %bb22 ]185 %phi32 = phi float [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ %fadd11, %bb7 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb13 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ 0.000000e+00, %bb20 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ], [ %fadd24, %bb22 ]186 ret void187}188