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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-cros-linux-gnu < %s | FileCheck %s3 4%struct.fe = type { [5 x i64] }5 6define i32 @test(i64 %0, i128 %1, i1 %2) {7; CHECK-LABEL: define i32 @test(8; CHECK-SAME: i64 [[TMP0:%.*]], i128 [[TMP1:%.*]], i1 [[TMP2:%.*]]) {9; CHECK-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_FE:%.*]], align 810; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 1611; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 2412; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 3213; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 814; CHECK-NEXT: br label %[[BB9:.*]]15; CHECK: [[BB9]]:16; CHECK-NEXT: [[TMP10:%.*]] = phi i64 [ undef, [[TMP3:%.*]] ], [ [[TMP29:%.*]], %[[BB9]] ]17; CHECK-NEXT: [[TMP11:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP26:%.*]], %[[BB9]] ]18; CHECK-NEXT: [[TMP12:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP23:%.*]], %[[BB9]] ]19; CHECK-NEXT: [[TMP13:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP20:%.*]], %[[BB9]] ]20; CHECK-NEXT: [[TMP14:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP17:%.*]], %[[BB9]] ]21; CHECK-NEXT: [[DOTSROA_14_0:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP52:%.*]], %[[BB9]] ]22; CHECK-NEXT: [[DOTSROA_11_0:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP50:%.*]], %[[BB9]] ]23; CHECK-NEXT: [[DOTSROA_8_0:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP57:%.*]], %[[BB9]] ]24; CHECK-NEXT: [[DOTSROA_4_0:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP56:%.*]], %[[BB9]] ]25; CHECK-NEXT: [[DOTSROA_0_0:%.*]] = phi i64 [ undef, [[TMP3]] ], [ [[TMP54:%.*]], %[[BB9]] ]26; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[DOTSROA_0_0]], [[TMP14]]27; CHECK-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP0]]28; CHECK-NEXT: [[TMP17]] = xor i64 [[TMP16]], 129; CHECK-NEXT: store i64 [[TMP17]], ptr [[TMP4]], align 830; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[DOTSROA_4_0]], [[TMP13]]31; CHECK-NEXT: [[TMP19:%.*]] = and i64 [[TMP18]], [[TMP0]]32; CHECK-NEXT: [[TMP20]] = xor i64 [[TMP19]], 133; CHECK-NEXT: store i64 [[TMP20]], ptr [[TMP8]], align 834; CHECK-NEXT: [[TMP21:%.*]] = xor i64 [[DOTSROA_8_0]], [[TMP12]]35; CHECK-NEXT: [[TMP22:%.*]] = and i64 [[TMP21]], [[TMP0]]36; CHECK-NEXT: [[TMP23]] = xor i64 [[TMP22]], 137; CHECK-NEXT: store i64 [[TMP23]], ptr [[TMP5]], align 838; CHECK-NEXT: [[TMP24:%.*]] = xor i64 [[DOTSROA_11_0]], [[TMP11]]39; CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], [[TMP0]]40; CHECK-NEXT: [[TMP26]] = xor i64 [[TMP25]], 141; CHECK-NEXT: store i64 [[TMP26]], ptr [[TMP6]], align 842; CHECK-NEXT: [[TMP27:%.*]] = xor i64 [[DOTSROA_14_0]], [[TMP10]]43; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP27]], [[TMP0]]44; CHECK-NEXT: [[TMP29]] = xor i64 [[TMP28]], 145; CHECK-NEXT: store i64 [[TMP29]], ptr [[TMP7]], align 846; CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr null, align 429496729647; CHECK-NEXT: [[TMP31:%.*]] = or i64 [[TMP19]], 148; CHECK-NEXT: [[TMP32:%.*]] = or i64 [[TMP16]], 149; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP17]], 150; CHECK-NEXT: [[TMP34:%.*]] = mul i64 [[TMP29]], 1951; CHECK-NEXT: [[TMP35:%.*]] = zext i64 [[TMP34]] to i12852; CHECK-NEXT: [[TMP36:%.*]] = mul i64 [[TMP26]], 1953; CHECK-NEXT: [[TMP37:%.*]] = zext i64 [[TMP36]] to i12854; CHECK-NEXT: [[TMP38:%.*]] = mul i64 [[TMP23]], 1955; CHECK-NEXT: [[TMP39:%.*]] = zext i64 [[TMP38]] to i12856; CHECK-NEXT: [[TMP40:%.*]] = mul nuw nsw i128 [[TMP39]], 2457; CHECK-NEXT: [[TMP41:%.*]] = zext i64 [[TMP32]] to i12858; CHECK-NEXT: [[TMP42:%.*]] = mul nuw i128 [[TMP37]], [[TMP41]]59; CHECK-NEXT: [[TMP43:%.*]] = zext i64 [[TMP31]] to i12860; CHECK-NEXT: [[TMP44:%.*]] = mul nuw i128 [[TMP35]], [[TMP43]]61; CHECK-NEXT: [[TMP45:%.*]] = zext i64 [[TMP33]] to i12862; CHECK-NEXT: [[TMP46:%.*]] = mul i128 [[TMP1]], [[TMP45]]63; CHECK-NEXT: [[TMP47:%.*]] = add i128 [[TMP40]], [[TMP46]]64; CHECK-NEXT: [[TMP48:%.*]] = add i128 [[TMP47]], [[TMP42]]65; CHECK-NEXT: [[TMP49:%.*]] = add i128 [[TMP48]], [[TMP44]]66; CHECK-NEXT: [[TMP50]] = and i64 [[TMP29]], 167; CHECK-NEXT: [[TMP51:%.*]] = trunc i128 [[TMP49]] to i6468; CHECK-NEXT: [[TMP52]] = and i64 [[TMP30]], 169; CHECK-NEXT: [[TMP53:%.*]] = add i64 [[TMP51]], 170; CHECK-NEXT: [[TMP54]] = and i64 [[TMP53]], 171; CHECK-NEXT: [[TMP55:%.*]] = lshr i64 [[TMP53]], 172; CHECK-NEXT: [[TMP56]] = and i64 [[TMP19]], 173; CHECK-NEXT: [[TMP57]] = or i64 [[TMP55]], 174; CHECK-NEXT: br i1 [[TMP2]], label %[[BB58:.*]], label %[[BB9]]75; CHECK: [[BB58]]:76; CHECK-NEXT: call void @g(ptr nonnull [[TMP4]])77; CHECK-NEXT: ret i32 078;79 %4 = alloca %struct.fe, align 880 %5 = getelementptr inbounds nuw i8, ptr %4, i64 1681 %6 = getelementptr inbounds nuw i8, ptr %4, i64 2482 %7 = getelementptr inbounds nuw i8, ptr %4, i64 3283 %8 = getelementptr inbounds nuw i8, ptr %4, i64 884 br label %985 869:87 %10 = phi i64 [ undef, %3 ], [ %29, %9 ]88 %11 = phi i64 [ undef, %3 ], [ %26, %9 ]89 %12 = phi i64 [ undef, %3 ], [ %23, %9 ]90 %13 = phi i64 [ undef, %3 ], [ %20, %9 ]91 %14 = phi i64 [ undef, %3 ], [ %17, %9 ]92 %.sroa.14.0 = phi i64 [ undef, %3 ], [ %52, %9 ]93 %.sroa.11.0 = phi i64 [ undef, %3 ], [ %50, %9 ]94 %.sroa.8.0 = phi i64 [ undef, %3 ], [ %57, %9 ]95 %.sroa.4.0 = phi i64 [ undef, %3 ], [ %56, %9 ]96 %.sroa.0.0 = phi i64 [ undef, %3 ], [ %54, %9 ]97 %15 = xor i64 %.sroa.0.0, %1498 %16 = and i64 %15, %099 %17 = xor i64 %16, 1100 store i64 %17, ptr %4, align 8101 %18 = xor i64 %.sroa.4.0, %13102 %19 = and i64 %18, %0103 %20 = xor i64 %19, 1104 store i64 %20, ptr %8, align 8105 %21 = xor i64 %.sroa.8.0, %12106 %22 = and i64 %21, %0107 %23 = xor i64 %22, 1108 store i64 %23, ptr %5, align 8109 %24 = xor i64 %.sroa.11.0, %11110 %25 = and i64 %24, %0111 %26 = xor i64 %25, 1112 store i64 %26, ptr %6, align 8113 %27 = xor i64 %.sroa.14.0, %10114 %28 = and i64 %27, %0115 %29 = xor i64 %28, 1116 store i64 %29, ptr %7, align 8117 %30 = load i64, ptr null, align 4294967296118 %31 = or i64 %19, 1119 %32 = or i64 %16, 1120 %33 = add i64 %17, 1121 %34 = mul i64 %29, 19122 %35 = zext i64 %34 to i128123 %36 = mul i64 %26, 19124 %37 = zext i64 %36 to i128125 %38 = mul i64 %23, 19126 %39 = zext i64 %38 to i128127 %40 = mul nuw nsw i128 %39, 24128 %41 = zext i64 %32 to i128129 %42 = mul nuw i128 %37, %41130 %43 = zext i64 %31 to i128131 %44 = mul nuw i128 %35, %43132 %45 = zext i64 %33 to i128133 %46 = mul i128 %1, %45134 %47 = add i128 %40, %46135 %48 = add i128 %47, %42136 %49 = add i128 %48, %44137 %50 = and i64 %29, 1138 %51 = trunc i128 %49 to i64139 %52 = and i64 %30, 1140 %53 = add i64 %51, 1141 %54 = and i64 %53, 1142 %55 = lshr i64 %53, 1143 %56 = and i64 %19, 1144 %57 = or i64 %55, 1145 br i1 %2, label %58, label %9146 14758:148 call void @g(ptr nonnull %4)149 ret i32 0150}151 152declare void @g(ptr)153 154