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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes=slp-vectorizer -mattr=+sse2 -S | FileCheck %s --check-prefix=SSE3; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes=slp-vectorizer -mattr=+avx -S | FileCheck %s --check-prefix=AVX4; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes=slp-vectorizer -mattr=+avx2 -S | FileCheck %s --check-prefix=AVX5 6%class.1 = type { %class.2 }7%class.2 = type { %"class.3" }8%"class.3" = type { %"struct.1", i64 }9%"struct.1" = type { [8 x i64] }10 11; Function Attrs: uwtable12define void @_ZN1C10SwitchModeEv(ptr %p, i64 %c) {13; SSE-LABEL: @_ZN1C10SwitchModeEv(14; SSE-NEXT: for.body.lr.ph.i:15; SSE-NEXT: [[BAR5:%.*]] = or i64 [[C:%.*]], 116; SSE-NEXT: store i64 [[BAR5]], ptr [[FOO_2:%.*]], align 817; SSE-NEXT: [[FOO_4:%.*]] = load i64, ptr [[FOO_2]], align 818; SSE-NEXT: [[FOO_3:%.*]] = getelementptr inbounds [[CLASS_1:%.*]], ptr [[FOO_2]], i64 0, i32 0, i32 0, i32 0, i32 0, i64 119; SSE-NEXT: [[FOO_5:%.*]] = load i64, ptr [[FOO_3]], align 820; SSE-NEXT: [[BAR6:%.*]] = load i64, ptr [[FOO_2]], align 821; SSE-NEXT: [[AND_1:%.*]] = and i64 [[BAR5]], [[FOO_4]]22; SSE-NEXT: [[AND_2:%.*]] = and i64 [[BAR6]], [[FOO_5]]23; SSE-NEXT: store i64 [[AND_1]], ptr [[FOO_2]], align 824; SSE-NEXT: [[BAR4:%.*]] = getelementptr inbounds [[CLASS_2:%.*]], ptr [[FOO_2]], i64 0, i32 0, i32 0, i32 0, i64 125; SSE-NEXT: store i64 [[AND_2]], ptr [[BAR4]], align 826; SSE-NEXT: ret void27;28; AVX-LABEL: @_ZN1C10SwitchModeEv(29; AVX-NEXT: for.body.lr.ph.i:30; AVX-NEXT: [[OR_1:%.*]] = or i64 [[C:%.*]], 131; AVX-NEXT: store i64 [[OR_1]], ptr [[P:%.*]], align 832; AVX-NEXT: [[BAR5:%.*]] = load i64, ptr [[P]], align 833; AVX-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[P]], align 834; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[OR_1]], i32 035; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[BAR5]], i32 136; AVX-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[TMP0]]37; AVX-NEXT: store <2 x i64> [[TMP3]], ptr [[P]], align 838; AVX-NEXT: ret void39;40for.body.lr.ph.i:41 %or.1 = or i64 %c, 142 store i64 %or.1, ptr %p, align 843 %foo.3 = load i64, ptr %p, align 844 %foo.2 = getelementptr inbounds %class.1, ptr %p, i64 0, i32 0, i32 0, i32 0, i32 0, i64 145 %foo.4 = load i64, ptr %foo.2, align 846 %bar5 = load i64, ptr %p, align 847 %and.2 = and i64 %or.1, %foo.348 %and.1 = and i64 %bar5, %foo.449 store i64 %and.2, ptr %p, align 850 %bar4 = getelementptr inbounds %class.2, ptr %p, i64 0, i32 0, i32 0, i32 0, i64 151 store i64 %and.1, ptr %bar4, align 852 ret void53}54 55; Function Attrs: norecurse nounwind uwtable56define void @pr35497(ptr %p, i64 %c) {57; SSE-LABEL: @pr35497(58; SSE-NEXT: entry:59; SSE-NEXT: [[TMP0:%.*]] = load i64, ptr [[P:%.*]], align 160; SSE-NEXT: [[AND:%.*]] = shl i64 [[TMP0]], 261; SSE-NEXT: [[SHL:%.*]] = and i64 [[AND]], 2062; SSE-NEXT: [[ADD:%.*]] = add i64 [[C:%.*]], [[C]]63; SSE-NEXT: store i64 [[ADD]], ptr [[P]], align 164; SSE-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 565; SSE-NEXT: [[AND_1:%.*]] = shl i64 [[C]], 266; SSE-NEXT: [[SHL_1:%.*]] = and i64 [[AND_1]], 2067; SSE-NEXT: [[SHR_1:%.*]] = lshr i64 [[C]], 668; SSE-NEXT: [[ADD_1:%.*]] = add nuw nsw i64 [[SHL]], [[SHR_1]]69; SSE-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 470; SSE-NEXT: [[SHR_2:%.*]] = lshr i64 [[C]], 671; SSE-NEXT: [[ADD_2:%.*]] = add nuw nsw i64 [[SHL_1]], [[SHR_2]]72; SSE-NEXT: [[AND_4:%.*]] = shl i64 [[ADD]], 273; SSE-NEXT: [[SHL_4:%.*]] = and i64 [[AND_4]], 2074; SSE-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 175; SSE-NEXT: store i64 [[ADD_1]], ptr [[ARRAYIDX2_5]], align 176; SSE-NEXT: [[AND_5:%.*]] = shl nuw nsw i64 [[ADD_1]], 277; SSE-NEXT: [[SHL_5:%.*]] = and i64 [[AND_5]], 2078; SSE-NEXT: [[SHR_5:%.*]] = lshr i64 [[ADD_1]], 679; SSE-NEXT: [[ADD_5:%.*]] = add nuw nsw i64 [[SHL_4]], [[SHR_5]]80; SSE-NEXT: store i64 [[ADD_5]], ptr [[ARRAYIDX2_1]], align 181; SSE-NEXT: store i64 [[ADD_2]], ptr [[P]], align 182; SSE-NEXT: [[SHR_6:%.*]] = lshr i64 [[ADD_2]], 683; SSE-NEXT: [[ADD_6:%.*]] = add nuw nsw i64 [[SHL_5]], [[SHR_6]]84; SSE-NEXT: store i64 [[ADD_6]], ptr [[ARRAYIDX2_2]], align 185; SSE-NEXT: ret void86;87; AVX-LABEL: @pr35497(88; AVX-NEXT: entry:89; AVX-NEXT: [[TMP0:%.*]] = load i64, ptr [[P:%.*]], align 190; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[C:%.*]], i32 091; AVX-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer92; AVX-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP2]], splat (i64 6)93; AVX-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 494; AVX-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 195; AVX-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[TMP0]], i32 196; AVX-NEXT: [[TMP5:%.*]] = shl <2 x i64> [[TMP4]], splat (i64 2)97; AVX-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP5]], splat (i64 20)98; AVX-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> [[TMP4]], <2 x i32> <i32 1, i32 2>99; AVX-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <2 x i32> <i32 1, i32 3>100; AVX-NEXT: [[TMP9:%.*]] = add <2 x i64> [[TMP7]], [[TMP8]]101; AVX-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1102; AVX-NEXT: store i64 [[TMP10]], ptr [[P]], align 1103; AVX-NEXT: [[TMP11:%.*]] = add nuw nsw <2 x i64> [[TMP6]], [[TMP3]]104; AVX-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0105; AVX-NEXT: store i64 [[TMP12]], ptr [[ARRAYIDX2_5]], align 1106; AVX-NEXT: [[TMP13:%.*]] = shl <2 x i64> [[TMP9]], splat (i64 2)107; AVX-NEXT: [[TMP14:%.*]] = and <2 x i64> [[TMP13]], splat (i64 20)108; AVX-NEXT: [[TMP15:%.*]] = extractelement <2 x i64> [[TMP11]], i32 0109; AVX-NEXT: store i64 [[TMP15]], ptr [[P]], align 1110; AVX-NEXT: [[TMP16:%.*]] = lshr <2 x i64> [[TMP11]], splat (i64 6)111; AVX-NEXT: [[TMP17:%.*]] = add nuw nsw <2 x i64> [[TMP14]], [[TMP16]]112; AVX-NEXT: store <2 x i64> [[TMP17]], ptr [[ARRAYIDX2_2]], align 1113; AVX-NEXT: ret void114;115entry:116 %0 = load i64, ptr %p, align 1117 %and = shl i64 %0, 2118 %shl = and i64 %and, 20119 %add = add i64 %c, %c120 store i64 %add, ptr %p, align 1121 %arrayidx2.1 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 5122 %and.1 = shl i64 %c, 2123 %shl.1 = and i64 %and.1, 20124 %shr.1 = lshr i64 %c, 6125 %add.1 = add nuw nsw i64 %shl, %shr.1126 %arrayidx2.2 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 4127 %shr.2 = lshr i64 %c, 6128 %add.2 = add nuw nsw i64 %shl.1, %shr.2129 %and.4 = shl i64 %add, 2130 %shl.4 = and i64 %and.4, 20131 %arrayidx2.5 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 1132 store i64 %add.1, ptr %arrayidx2.5, align 1133 %and.5 = shl nuw nsw i64 %add.1, 2134 %shl.5 = and i64 %and.5, 20135 %shr.5 = lshr i64 %add.1, 6136 %add.5 = add nuw nsw i64 %shl.4, %shr.5137 store i64 %add.5, ptr %arrayidx2.1, align 1138 store i64 %add.2, ptr %p, align 1139 %shr.6 = lshr i64 %add.2, 6140 %add.6 = add nuw nsw i64 %shl.5, %shr.6141 store i64 %add.6, ptr %arrayidx2.2, align 1142 ret void143}144