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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=i686-pc-win32 -mcpu=corei7-avx | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux"6 7@e = dso_local global i32 0, align 48@f = dso_local local_unnamed_addr global i32 0, align 49@d = dso_local global i32 0, align 410@c = dso_local global i32 0, align 411@b = dso_local global i32 0, align 412@a = dso_local local_unnamed_addr global i32 0, align 413 14define dso_local i32 @main() {15; CHECK-LABEL: @main(16; CHECK-NEXT: entry:17; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @e, align 418; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @f, align 419; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]]20; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]21; CHECK: if.then:22; CHECK-NEXT: [[TMP2:%.*]] = load volatile i32, ptr @d, align 423; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, ptr @c, align 424; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP3]], 025; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]26; CHECK: lor.rhs:27; CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @d, align 428; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i32 [[TMP4]], 029; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL1]] to i3230; CHECK-NEXT: br label [[LOR_END]]31; CHECK: lor.end:32; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ 1, [[IF_THEN]] ], [ [[PHI_CAST]], [[LOR_RHS]] ]33; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP1]], 034; CHECK-NEXT: [[LAND_EXT:%.*]] = zext i1 [[TOBOOL2]] to i3235; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP5]], [[LAND_EXT]]36; CHECK-NEXT: store volatile i32 [[OR]], ptr @b, align 437; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP1]], [[TMP2]]38; CHECK-NEXT: [[TMP6:%.*]] = load volatile i32, ptr @d, align 439; CHECK-NEXT: [[TOBOOL4_NOT:%.*]] = icmp eq i32 [[TMP6]], 040; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label [[LAND_END7:%.*]], label [[LAND_RHS5:%.*]]41; CHECK: land.rhs5:42; CHECK-NEXT: [[TMP7:%.*]] = load volatile i32, ptr @c, align 443; CHECK-NEXT: [[TOBOOL6:%.*]] = icmp ne i32 [[TMP7]], 044; CHECK-NEXT: [[PHI_CAST11:%.*]] = zext i1 [[TOBOOL6]] to i3245; CHECK-NEXT: br label [[LAND_END7]]46; CHECK: land.end7:47; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ 0, [[LOR_END]] ], [ [[PHI_CAST11]], [[LAND_RHS5]] ]48; CHECK-NEXT: [[OR9:%.*]] = or i32 [[TMP8]], [[DIV]]49; CHECK-NEXT: store i32 [[OR9]], ptr @a, align 450; CHECK-NEXT: br label [[IF_END]]51; CHECK: if.end:52; CHECK-NEXT: ret i32 053;54entry:55 %0 = load volatile i32, ptr @e, align 456 %1 = load i32, ptr @f, align 457 %cmp = icmp sgt i32 %0, %158 br i1 %cmp, label %if.then, label %if.end59 60if.then: ; preds = %entry61 %2 = load volatile i32, ptr @d, align 462 %3 = load volatile i32, ptr @c, align 463 %tobool.not = icmp eq i32 %3, 064 br i1 %tobool.not, label %lor.rhs, label %lor.end65 66lor.rhs: ; preds = %if.then67 %4 = load volatile i32, ptr @d, align 468 %tobool1 = icmp ne i32 %4, 069 %phi.cast = zext i1 %tobool1 to i3270 br label %lor.end71 72lor.end: ; preds = %lor.rhs, %if.then73 %5 = phi i32 [ 1, %if.then ], [ %phi.cast, %lor.rhs ]74 %tobool2 = icmp ne i32 %1, 075 %land.ext = zext i1 %tobool2 to i3276 %or = or i32 %5, %land.ext77 store volatile i32 %or, ptr @b, align 478 %div = sdiv i32 %1, %279 %6 = load volatile i32, ptr @d, align 480 %tobool4.not = icmp eq i32 %6, 081 br i1 %tobool4.not, label %land.end7, label %land.rhs582 83land.rhs5: ; preds = %lor.end84 %7 = load volatile i32, ptr @c, align 485 %tobool6 = icmp ne i32 %7, 086 %phi.cast11 = zext i1 %tobool6 to i3287 br label %land.end788 89land.end7: ; preds = %land.rhs5, %lor.end90 %8 = phi i32 [ 0, %lor.end ], [ %phi.cast11, %land.rhs5 ]91 %or9 = or i32 %8, %div92 store i32 %or9, ptr @a, align 493 br label %if.end94 95if.end: ; preds = %land.end7, %entry96 ret i32 097}98