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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX3; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,SSE4; REQUIRES: asserts5 6; int test_add(unsigned int *p) {7; int result = 0;8; for (int i = 0; i < 8; i++)9; result += p[i];10; return result;11; }12 13; Vector cost is 5, Scalar cost is 714; AVX: Adding cost -2 for reduction of n=8 [ %0 = load i32, ptr %p, align 4, ..] (It is a splitting reduction)15; Vector cost is 4, Scalar cost is 716; SSE: Adding cost -3 for reduction of n=8 [ %0 = load i32, ptr %p, align 4, ..] (It is a splitting reduction)17define i32 @test_add(ptr nocapture readonly %p) {18; CHECK-LABEL: @test_add(19; CHECK-NEXT: entry:20; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 421; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP1]])22; CHECK-NEXT: ret i32 [[TMP2]]23;24entry:25 %0 = load i32, ptr %p, align 426 %arrayidx.1 = getelementptr inbounds i32, ptr %p, i64 127 %1 = load i32, ptr %arrayidx.1, align 428 %mul.18 = add i32 %0, %129 %arrayidx.2 = getelementptr inbounds i32, ptr %p, i64 230 %2 = load i32, ptr %arrayidx.2, align 431 %mul.29 = add i32 %2, %mul.1832 %arrayidx.3 = getelementptr inbounds i32, ptr %p, i64 333 %3 = load i32, ptr %arrayidx.3, align 434 %mul.310 = add i32 %3, %mul.2935 %arrayidx.4 = getelementptr inbounds i32, ptr %p, i64 436 %4 = load i32, ptr %arrayidx.4, align 437 %mul.411 = add i32 %4, %mul.31038 %arrayidx.5 = getelementptr inbounds i32, ptr %p, i64 539 %5 = load i32, ptr %arrayidx.5, align 440 %mul.512 = add i32 %5, %mul.41141 %arrayidx.6 = getelementptr inbounds i32, ptr %p, i64 642 %6 = load i32, ptr %arrayidx.6, align 443 %mul.613 = add i32 %6, %mul.51244 %arrayidx.7 = getelementptr inbounds i32, ptr %p, i64 745 %7 = load i32, ptr %arrayidx.7, align 446 %mul.714 = add i32 %7, %mul.61347 ret i32 %mul.71448}49 50; int test_mul(unsigned int *p) {51; int result = 0;52; for (int i = 0; i < 8; i++)53; result *= p[i];54; return result;55; }56 57define i32 @test_mul(ptr nocapture readonly %p) {58; AVX-LABEL: @test_mul(59; AVX-NEXT: entry:60; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 461; AVX-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP1]])62; AVX-NEXT: ret i32 [[TMP2]]63;64; SSE-LABEL: @test_mul(65; SSE-NEXT: entry:66; SSE-NEXT: [[TMP0:%.*]] = load i32, ptr [[P:%.*]], align 467; SSE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 168; SSE-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 469; SSE-NEXT: [[MUL_18:%.*]] = mul i32 [[TMP1]], [[TMP0]]70; SSE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 271; SSE-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 472; SSE-NEXT: [[MUL_29:%.*]] = mul i32 [[TMP2]], [[MUL_18]]73; SSE-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 374; SSE-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 475; SSE-NEXT: [[MUL_310:%.*]] = mul i32 [[TMP3]], [[MUL_29]]76; SSE-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 477; SSE-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 478; SSE-NEXT: [[MUL_411:%.*]] = mul i32 [[TMP4]], [[MUL_310]]79; SSE-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 580; SSE-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 481; SSE-NEXT: [[MUL_512:%.*]] = mul i32 [[TMP5]], [[MUL_411]]82; SSE-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 683; SSE-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 484; SSE-NEXT: [[MUL_613:%.*]] = mul i32 [[TMP6]], [[MUL_512]]85; SSE-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 786; SSE-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 487; SSE-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]]88; SSE-NEXT: ret i32 [[MUL_714]]89;90entry:91 %0 = load i32, ptr %p, align 492 %arrayidx.1 = getelementptr inbounds i32, ptr %p, i64 193 %1 = load i32, ptr %arrayidx.1, align 494 %mul.18 = mul i32 %1, %095 %arrayidx.2 = getelementptr inbounds i32, ptr %p, i64 296 %2 = load i32, ptr %arrayidx.2, align 497 %mul.29 = mul i32 %2, %mul.1898 %arrayidx.3 = getelementptr inbounds i32, ptr %p, i64 399 %3 = load i32, ptr %arrayidx.3, align 4100 %mul.310 = mul i32 %3, %mul.29101 %arrayidx.4 = getelementptr inbounds i32, ptr %p, i64 4102 %4 = load i32, ptr %arrayidx.4, align 4103 %mul.411 = mul i32 %4, %mul.310104 %arrayidx.5 = getelementptr inbounds i32, ptr %p, i64 5105 %5 = load i32, ptr %arrayidx.5, align 4106 %mul.512 = mul i32 %5, %mul.411107 %arrayidx.6 = getelementptr inbounds i32, ptr %p, i64 6108 %6 = load i32, ptr %arrayidx.6, align 4109 %mul.613 = mul i32 %6, %mul.512110 %arrayidx.7 = getelementptr inbounds i32, ptr %p, i64 7111 %7 = load i32, ptr %arrayidx.7, align 4112 %mul.714 = mul i32 %7, %mul.613113 ret i32 %mul.714114}115 116; int test_and(unsigned int *p) {117; int result = 0;118; for (int i = 0; i < 8; i++)119; result &= p[i];120; return result;121; }122 123define i32 @test_and(ptr nocapture readonly %p) {124; CHECK-LABEL: @test_and(125; CHECK-NEXT: entry:126; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 4127; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> [[TMP1]])128; CHECK-NEXT: ret i32 [[TMP2]]129;130entry:131 %0 = load i32, ptr %p, align 4132 %arrayidx.1 = getelementptr inbounds i32, ptr %p, i64 1133 %1 = load i32, ptr %arrayidx.1, align 4134 %mul.18 = and i32 %1, %0135 %arrayidx.2 = getelementptr inbounds i32, ptr %p, i64 2136 %2 = load i32, ptr %arrayidx.2, align 4137 %mul.29 = and i32 %2, %mul.18138 %arrayidx.3 = getelementptr inbounds i32, ptr %p, i64 3139 %3 = load i32, ptr %arrayidx.3, align 4140 %mul.310 = and i32 %3, %mul.29141 %arrayidx.4 = getelementptr inbounds i32, ptr %p, i64 4142 %4 = load i32, ptr %arrayidx.4, align 4143 %mul.411 = and i32 %4, %mul.310144 %arrayidx.5 = getelementptr inbounds i32, ptr %p, i64 5145 %5 = load i32, ptr %arrayidx.5, align 4146 %mul.512 = and i32 %5, %mul.411147 %arrayidx.6 = getelementptr inbounds i32, ptr %p, i64 6148 %6 = load i32, ptr %arrayidx.6, align 4149 %mul.613 = and i32 %6, %mul.512150 %arrayidx.7 = getelementptr inbounds i32, ptr %p, i64 7151 %7 = load i32, ptr %arrayidx.7, align 4152 %mul.714 = and i32 %7, %mul.613153 ret i32 %mul.714154}155 156; int test_or(unsigned int *p) {157; int result = 0;158; for (int i = 0; i < 8; i++)159; result |= p[i];160; return result;161; }162 163define i32 @test_or(ptr nocapture readonly %p) {164; CHECK-LABEL: @test_or(165; CHECK-NEXT: entry:166; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 4167; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP1]])168; CHECK-NEXT: ret i32 [[TMP2]]169;170entry:171 %0 = load i32, ptr %p, align 4172 %arrayidx.1 = getelementptr inbounds i32, ptr %p, i64 1173 %1 = load i32, ptr %arrayidx.1, align 4174 %mul.18 = or i32 %1, %0175 %arrayidx.2 = getelementptr inbounds i32, ptr %p, i64 2176 %2 = load i32, ptr %arrayidx.2, align 4177 %mul.29 = or i32 %2, %mul.18178 %arrayidx.3 = getelementptr inbounds i32, ptr %p, i64 3179 %3 = load i32, ptr %arrayidx.3, align 4180 %mul.310 = or i32 %3, %mul.29181 %arrayidx.4 = getelementptr inbounds i32, ptr %p, i64 4182 %4 = load i32, ptr %arrayidx.4, align 4183 %mul.411 = or i32 %4, %mul.310184 %arrayidx.5 = getelementptr inbounds i32, ptr %p, i64 5185 %5 = load i32, ptr %arrayidx.5, align 4186 %mul.512 = or i32 %5, %mul.411187 %arrayidx.6 = getelementptr inbounds i32, ptr %p, i64 6188 %6 = load i32, ptr %arrayidx.6, align 4189 %mul.613 = or i32 %6, %mul.512190 %arrayidx.7 = getelementptr inbounds i32, ptr %p, i64 7191 %7 = load i32, ptr %arrayidx.7, align 4192 %mul.714 = or i32 %7, %mul.613193 ret i32 %mul.714194}195 196; int test_xor(unsigned int *p) {197; int result = 0;198; for (int i = 0; i < 8; i++)199; result ^= p[i];200; return result;201; }202 203define i32 @test_xor(ptr nocapture readonly %p) {204; CHECK-LABEL: @test_xor(205; CHECK-NEXT: entry:206; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 4207; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> [[TMP1]])208; CHECK-NEXT: ret i32 [[TMP2]]209;210entry:211 %0 = load i32, ptr %p, align 4212 %arrayidx.1 = getelementptr inbounds i32, ptr %p, i64 1213 %1 = load i32, ptr %arrayidx.1, align 4214 %mul.18 = xor i32 %1, %0215 %arrayidx.2 = getelementptr inbounds i32, ptr %p, i64 2216 %2 = load i32, ptr %arrayidx.2, align 4217 %mul.29 = xor i32 %2, %mul.18218 %arrayidx.3 = getelementptr inbounds i32, ptr %p, i64 3219 %3 = load i32, ptr %arrayidx.3, align 4220 %mul.310 = xor i32 %3, %mul.29221 %arrayidx.4 = getelementptr inbounds i32, ptr %p, i64 4222 %4 = load i32, ptr %arrayidx.4, align 4223 %mul.411 = xor i32 %4, %mul.310224 %arrayidx.5 = getelementptr inbounds i32, ptr %p, i64 5225 %5 = load i32, ptr %arrayidx.5, align 4226 %mul.512 = xor i32 %5, %mul.411227 %arrayidx.6 = getelementptr inbounds i32, ptr %p, i64 6228 %6 = load i32, ptr %arrayidx.6, align 4229 %mul.613 = xor i32 %6, %mul.512230 %arrayidx.7 = getelementptr inbounds i32, ptr %p, i64 7231 %7 = load i32, ptr %arrayidx.7, align 4232 %mul.714 = xor i32 %7, %mul.613233 ret i32 %mul.714234}235 236define i32 @PR37731(ptr noalias nocapture dereferenceable(16) %self) unnamed_addr #0 {237; CHECK-LABEL: @PR37731(238; CHECK-NEXT: entry:239; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[SELF:%.*]], align 16240; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[TMP0]], <i32 6, i32 2, i32 13, i32 3>241; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], [[TMP0]]242; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP2]], <i32 13, i32 27, i32 21, i32 12>243; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i32> [[TMP0]], <i32 -2, i32 -8, i32 -16, i32 -128>244; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i32> [[TMP4]], <i32 18, i32 2, i32 7, i32 13>245; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP3]], [[TMP5]]246; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr [[SELF]], align 16247; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP6]])248; CHECK-NEXT: ret i32 [[TMP7]]249;250entry:251 %0 = load <4 x i32>, ptr %self, align 16252 %1 = shl <4 x i32> %0, <i32 6, i32 2, i32 13, i32 3>253 %2 = xor <4 x i32> %1, %0254 %3 = lshr <4 x i32> %2, <i32 13, i32 27, i32 21, i32 12>255 %4 = and <4 x i32> %0, <i32 -2, i32 -8, i32 -16, i32 -128>256 %5 = shl <4 x i32> %4, <i32 18, i32 2, i32 7, i32 13>257 %6 = xor <4 x i32> %3, %5258 store <4 x i32> %6, ptr %self, align 16259 %7 = extractelement <4 x i32> %6, i32 0260 %8 = extractelement <4 x i32> %6, i32 1261 %9 = xor i32 %7, %8262 %10 = extractelement <4 x i32> %6, i32 2263 %11 = xor i32 %9, %10264 %12 = extractelement <4 x i32> %6, i32 3265 %13 = xor i32 %11, %12266 ret i32 %13267}268