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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=x86_64-pc-linux-gnu -mcpu=generic -mattr=sse2 -passes=slp-vectorizer -pass-remarks-output=%t < %s -slp-threshold=-2 | FileCheck %s3; RUN: FileCheck --input-file=%t --check-prefix=YAML %s4 5define void @fextr(ptr %ptr) {6; CHECK-LABEL: @fextr(7; CHECK-NEXT: entry:8; CHECK-NEXT: [[LD:%.*]] = load <8 x i16>, ptr undef, align 169; CHECK-NEXT: br label [[T:%.*]]10; CHECK: t:11; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x i16> [[LD]], <8 x i16> <i16 poison, i16 undef, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>, <8 x i32> <i32 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>12; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i16> [[LD]], [[TMP0]]13; CHECK-NEXT: store <8 x i16> [[TMP1]], ptr [[PTR:%.*]], align 214; CHECK-NEXT: ret void15;16; YAML: Pass: slp-vectorizer17; YAML-NEXT: Name: StoresVectorized18; YAML-NEXT: Function: fextr19; YAML-NEXT: Args:20; YAML-NEXT: - String: 'Stores SLP vectorized with cost '21; YAML-NEXT: - Cost: '-21'22; YAML-NEXT: - String: ' and with tree size '23; YAML-NEXT: - TreeSize: '4'24 25entry:26 %LD = load <8 x i16>, ptr undef27 %V0 = extractelement <8 x i16> %LD, i32 028 br label %t29 30t:31 %V1 = extractelement <8 x i16> %LD, i32 132 %V2 = extractelement <8 x i16> %LD, i32 233 %V3 = extractelement <8 x i16> %LD, i32 334 %V4 = extractelement <8 x i16> %LD, i32 435 %V5 = extractelement <8 x i16> %LD, i32 536 %V6 = extractelement <8 x i16> %LD, i32 637 %V7 = extractelement <8 x i16> %LD, i32 738 %P1 = getelementptr inbounds i16, ptr %ptr, i64 139 %P2 = getelementptr inbounds i16, ptr %ptr, i64 240 %P3 = getelementptr inbounds i16, ptr %ptr, i64 341 %P4 = getelementptr inbounds i16, ptr %ptr, i64 442 %P5 = getelementptr inbounds i16, ptr %ptr, i64 543 %P6 = getelementptr inbounds i16, ptr %ptr, i64 644 %P7 = getelementptr inbounds i16, ptr %ptr, i64 745 %A0 = add i16 %V0, %V046 %A1 = add i16 %V1, undef47 %A2 = add i16 %V2, %V048 %A3 = add i16 %V3, %V049 %A4 = add i16 %V4, %V050 %A5 = add i16 %V5, %V051 %A6 = add i16 %V6, %V052 %A7 = add i16 %V7, %V053 store i16 %A0, ptr %ptr, align 254 store i16 %A1, ptr %P1, align 255 store i16 %A2, ptr %P2, align 256 store i16 %A3, ptr %P3, align 257 store i16 %A4, ptr %P4, align 258 store i16 %A5, ptr %P5, align 259 store i16 %A6, ptr %P6, align 260 store i16 %A7, ptr %P7, align 261 ret void62}63