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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-revec -slp-max-reg-size=1024 -slp-threshold=-100 < %s | FileCheck %s3 4define <4 x i16> @test() {5; CHECK-LABEL: define <4 x i16> @test() {6; CHECK-NEXT: [[ENTRY:.*:]]7; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> zeroinitializer, <4 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>8; CHECK-NEXT: [[TMP1:%.*]] = add <16 x i16> [[TMP0]], zeroinitializer9; CHECK-NEXT: [[RDX_OP:%.*]] = or <16 x i16> zeroinitializer, [[TMP1]]10; CHECK-NEXT: [[TMP36:%.*]] = shufflevector <16 x i16> [[RDX_OP]], <16 x i16> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>11; CHECK-NEXT: [[TMP37:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP36]])12; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i16> poison, i16 [[TMP37]], i64 013; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <16 x i16> [[RDX_OP]], <16 x i16> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>14; CHECK-NEXT: [[TMP40:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP39]])15; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x i16> [[TMP38]], i16 [[TMP40]], i64 116; CHECK-NEXT: [[TMP42:%.*]] = shufflevector <16 x i16> [[RDX_OP]], <16 x i16> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>17; CHECK-NEXT: [[TMP43:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP42]])18; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i16> [[TMP41]], i16 [[TMP43]], i64 219; CHECK-NEXT: [[TMP45:%.*]] = shufflevector <16 x i16> [[RDX_OP]], <16 x i16> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>20; CHECK-NEXT: [[TMP46:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP45]])21; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i16> [[TMP44]], i16 [[TMP46]], i64 322; CHECK-NEXT: [[OP_RDX9:%.*]] = or <4 x i16> [[TMP47]], zeroinitializer23; CHECK-NEXT: ret <4 x i16> [[OP_RDX9]]24;25entry:26 %subi = add <4 x i16> zeroinitializer, zeroinitializer27 %sub40.i = add <4 x i16> %subi, zeroinitializer28 %sub41.i = add <4 x i16> %subi, zeroinitializer29 %sub42.i = add <4 x i16> %subi, zeroinitializer30 %sub43.i = add <4 x i16> %subi, zeroinitializer31 %sub44.i = add <4 x i16> %subi, zeroinitializer32 %sub45.i = add <4 x i16> %subi, zeroinitializer33 %sub46.i = add <4 x i16> zeroinitializer, zeroinitializer34 %sub47.i = add <4 x i16> zeroinitializer, zeroinitializer35 %sub48.i = add <4 x i16> zeroinitializer, zeroinitializer36 %sub49.i = add <4 x i16> zeroinitializer, zeroinitializer37 %or40.i = or <4 x i16> %sub40.i, %sub41.i38 %or41.i = or <4 x i16> %or40.i, %sub42.i39 %or42.i = or <4 x i16> %or41.i, %sub43.i40 %or43.i = or <4 x i16> %or42.i, %sub44.i41 %or44.i = or <4 x i16> %or43.i, %sub45.i42 %or45.i = or <4 x i16> %or44.i, %sub46.i43 %or46.i = or <4 x i16> %or45.i, %sub47.i44 %or47.i = or <4 x i16> %or46.i, %sub48.i45 %or48.i = or <4 x i16> %or47.i, %sub49.i46 %or50.i = or <4 x i16> %or48.i, %subi47 %subii = add <4 x i16> zeroinitializer, zeroinitializer48 %subi16.i = add <4 x i16> %subii, zeroinitializer49 %subi17.i = add <4 x i16> %subii, zeroinitializer50 %0 = or <4 x i16> %subi16.i, %subi17.i51 %1 = or <4 x i16> %0, %or50.i52 ret <4 x i16> %153}54