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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s3 4define i1 @test() {5; CHECK-LABEL: define i1 @test() {6; CHECK-NEXT: [[ENTRY:.*:]]7; CHECK-NEXT: [[H_PROMOTED118_I_FR:%.*]] = freeze i32 18; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i32 29; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> zeroinitializer, [[TMP0]]10; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i32 011; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> zeroinitializer, [[TMP3]]12; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 0>13; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]14; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i32> [[TMP5]], <i32 0, i32 1, i32 1, i32 1>15; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[TMP6]], <i32 1, i32 0, i32 0, i32 0>16; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])17; CHECK-NEXT: [[OP_RDX:%.*]] = or i1 [[TMP8]], false18; CHECK-NEXT: ret i1 [[OP_RDX]]19;20entry:21 %h.promoted118.i.fr = freeze i32 122 %invariant.op.i51 = add i32 %h.promoted118.i.fr, 023 %conv25.i = xor i32 0, 024 %add.i.i = add i32 %conv25.i, %h.promoted118.i.fr25 %sext.i.mask = and i32 %add.i.i, 026 %cmp27.i = icmp eq i32 %sext.i.mask, 127 %0 = or i1 %cmp27.i, false28 %conv25.i.1 = add i32 0, 029 %add.i.i.1 = add i32 %conv25.i.1, %h.promoted118.i.fr30 %sext.i.1.mask = and i32 %add.i.i.1, 131 %cmp27.i.1 = icmp eq i32 %sext.i.1.mask, 032 %conv25.1.i.1 = xor i32 0, 033 %add.i.1.i.1 = add i32 %conv25.1.i.1, %h.promoted118.i.fr34 %sext.1.i.1.mask = and i32 %add.i.1.i.1, 135 %cmp27.1.i.1 = icmp eq i32 %sext.1.i.1.mask, 036 %add.i.2.reass.i.1 = add i32 %invariant.op.i51, %conv25.i.137 %sext.2.i.1.mask = and i32 %add.i.2.reass.i.1, 138 %cmp27.2.i.1 = icmp eq i32 %sext.2.i.1.mask, 039 %1 = or i1 %cmp27.1.i.1, %cmp27.2.i.140 %2 = or i1 %cmp27.i.1, %141 %3 = or i1 %0, %242 ret i1 %343}44