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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer,dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"5target triple = "x86_64-apple-macosx10.8.0"6 7; Simple 3-pair chain with loads and stores8define void @test1(ptr %a, ptr %b, ptr %c) {9; CHECK-LABEL: @test1(10; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[A:%.*]], align 811; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[B:%.*]], align 812; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]13; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[C:%.*]], align 814; CHECK-NEXT: ret void15;16 %i0 = load double, ptr %a, align 817 %i1 = load double, ptr %b, align 818 %mul = fmul double %i0, %i119 %arrayidx3 = getelementptr inbounds double, ptr %a, i64 120 %i3 = load double, ptr %arrayidx3, align 821 %arrayidx4 = getelementptr inbounds double, ptr %b, i64 122 %i4 = load double, ptr %arrayidx4, align 823 %mul5 = fmul double %i3, %i424 store double %mul, ptr %c, align 825 %arrayidx5 = getelementptr inbounds double, ptr %c, i64 126 store double %mul5, ptr %arrayidx5, align 827 ret void28}29 30; Simple 3-pair chain with loads and stores, obfuscated with bitcasts31define void @test2(ptr %a, ptr %b, ptr %e) {32; CHECK-LABEL: @test2(33; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[A:%.*]], align 834; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[B:%.*]], align 835; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]36; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[E:%.*]], align 837; CHECK-NEXT: ret void38;39 %i0 = load double, ptr %a, align 840 %i1 = load double, ptr %b, align 841 %mul = fmul double %i0, %i142 %arrayidx3 = getelementptr inbounds double, ptr %a, i64 143 %i3 = load double, ptr %arrayidx3, align 844 %arrayidx4 = getelementptr inbounds double, ptr %b, i64 145 %i4 = load double, ptr %arrayidx4, align 846 %mul5 = fmul double %i3, %i447 store double %mul, ptr %e, align 848 %carrayidx5 = getelementptr inbounds i8, ptr %e, i64 849 store double %mul5, ptr %carrayidx5, align 850 ret void51}52 53; Don't vectorize volatile loads.54define void @test_volatile_load(ptr %a, ptr %b, ptr %c) {55; CHECK-LABEL: @test_volatile_load(56; CHECK-NEXT: [[I0:%.*]] = load volatile double, ptr [[A:%.*]], align 857; CHECK-NEXT: [[I1:%.*]] = load volatile double, ptr [[B:%.*]], align 858; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, ptr [[A]], i64 159; CHECK-NEXT: [[I3:%.*]] = load double, ptr [[ARRAYIDX3]], align 860; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, ptr [[B]], i64 161; CHECK-NEXT: [[I4:%.*]] = load double, ptr [[ARRAYIDX4]], align 862; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[I0]], i32 063; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[I3]], i32 164; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[I1]], i32 065; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[I4]], i32 166; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]67; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[C:%.*]], align 868; CHECK-NEXT: ret void69;70 %i0 = load volatile double, ptr %a, align 871 %i1 = load volatile double, ptr %b, align 872 %mul = fmul double %i0, %i173 %arrayidx3 = getelementptr inbounds double, ptr %a, i64 174 %i3 = load double, ptr %arrayidx3, align 875 %arrayidx4 = getelementptr inbounds double, ptr %b, i64 176 %i4 = load double, ptr %arrayidx4, align 877 %mul5 = fmul double %i3, %i478 store double %mul, ptr %c, align 879 %arrayidx5 = getelementptr inbounds double, ptr %c, i64 180 store double %mul5, ptr %arrayidx5, align 881 ret void82}83 84; Don't vectorize volatile stores.85define void @test_volatile_store(ptr %a, ptr %b, ptr %c) {86; CHECK-LABEL: @test_volatile_store(87; CHECK-NEXT: [[I0:%.*]] = load double, ptr [[A:%.*]], align 888; CHECK-NEXT: [[I1:%.*]] = load double, ptr [[B:%.*]], align 889; CHECK-NEXT: [[MUL:%.*]] = fmul double [[I0]], [[I1]]90; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, ptr [[A]], i64 191; CHECK-NEXT: [[I3:%.*]] = load double, ptr [[ARRAYIDX3]], align 892; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, ptr [[B]], i64 193; CHECK-NEXT: [[I4:%.*]] = load double, ptr [[ARRAYIDX4]], align 894; CHECK-NEXT: [[MUL5:%.*]] = fmul double [[I3]], [[I4]]95; CHECK-NEXT: store volatile double [[MUL]], ptr [[C:%.*]], align 896; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, ptr [[C]], i64 197; CHECK-NEXT: store volatile double [[MUL5]], ptr [[ARRAYIDX5]], align 898; CHECK-NEXT: ret void99;100 %i0 = load double, ptr %a, align 8101 %i1 = load double, ptr %b, align 8102 %mul = fmul double %i0, %i1103 %arrayidx3 = getelementptr inbounds double, ptr %a, i64 1104 %i3 = load double, ptr %arrayidx3, align 8105 %arrayidx4 = getelementptr inbounds double, ptr %b, i64 1106 %i4 = load double, ptr %arrayidx4, align 8107 %mul5 = fmul double %i3, %i4108 store volatile double %mul, ptr %c, align 8109 %arrayidx5 = getelementptr inbounds double, ptr %c, i64 1110 store volatile double %mul5, ptr %arrayidx5, align 8111 ret void112}113 114