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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -S -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=SSE43; RUN: opt -passes=slp-vectorizer -S -mcpu=bdver2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX4; RUN: opt -passes=slp-vectorizer -S -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX25 6; This test checks for a case when a horizontal reduction of floating-point7; adds may look profitable, but is not because it eliminates generation of8; floating-point FMAs that would be more profitable.9 10define void @hr() {11; SSE4-LABEL: @hr(12; SSE4-NEXT: br label [[LOOP:%.*]]13; SSE4: loop:14; SSE4-NEXT: [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[OP_RDX:%.*]], [[LOOP]] ]15; SSE4-NEXT: [[CVT0:%.*]] = uitofp i16 0 to double16; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i32 017; SSE4-NEXT: [[TMP2:%.*]] = fmul fast <4 x double> zeroinitializer, [[TMP1]]18; SSE4-NEXT: [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP2]])19; SSE4-NEXT: [[OP_RDX]] = fadd fast double [[TMP3]], [[PHI0]]20; SSE4-NEXT: br i1 true, label [[EXIT:%.*]], label [[LOOP]]21; SSE4: exit:22; SSE4-NEXT: ret void23;24; AVX-LABEL: @hr(25; AVX-NEXT: br label [[LOOP:%.*]]26; AVX: loop:27; AVX-NEXT: [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[ADD3:%.*]], [[LOOP]] ]28; AVX-NEXT: [[CVT0:%.*]] = uitofp i16 0 to double29; AVX-NEXT: [[MUL0:%.*]] = fmul fast double 0.000000e+00, [[CVT0]]30; AVX-NEXT: [[ADD0:%.*]] = fadd fast double [[MUL0]], [[PHI0]]31; AVX-NEXT: [[ADD1:%.*]] = fadd fast double 0.000000e+00, [[ADD0]]32; AVX-NEXT: [[ADD2:%.*]] = fadd fast double 0.000000e+00, [[ADD1]]33; AVX-NEXT: [[ADD3]] = fadd fast double 0.000000e+00, [[ADD2]]34; AVX-NEXT: br i1 true, label [[EXIT:%.*]], label [[LOOP]]35; AVX: exit:36; AVX-NEXT: ret void37;38; AVX2-LABEL: @hr(39; AVX2-NEXT: br label [[LOOP:%.*]]40; AVX2: loop:41; AVX2-NEXT: [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[OP_RDX:%.*]], [[LOOP]] ]42; AVX2-NEXT: [[CVT0:%.*]] = uitofp i16 0 to double43; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i32 044; AVX2-NEXT: [[TMP2:%.*]] = fmul fast <4 x double> zeroinitializer, [[TMP1]]45; AVX2-NEXT: [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP2]])46; AVX2-NEXT: [[OP_RDX]] = fadd fast double [[TMP3]], [[PHI0]]47; AVX2-NEXT: br i1 true, label [[EXIT:%.*]], label [[LOOP]]48; AVX2: exit:49; AVX2-NEXT: ret void50;51 br label %loop52 53loop:54 %phi0 = phi double [ 0.000000e+00, %0 ], [ %add3, %loop ]55 %cvt0 = uitofp i16 0 to double56 %mul0 = fmul fast double 0.000000e+00, %cvt057 %add0 = fadd fast double %mul0, %phi058 %mul1 = fmul fast double 0.000000e+00, 0.000000e+0059 %add1 = fadd fast double %mul1, %add060 %mul2 = fmul fast double 0.000000e+00, 0.000000e+0061 %add2 = fadd fast double %mul2, %add162 %mul3 = fmul fast double 0.000000e+00, 0.000000e+0063 %add3 = fadd fast double %mul3, %add264 br i1 true, label %exit, label %loop65 66exit:67 ret void68}69 70; This test checks for a case when either a horizontal reduction of71; floating-point adds, or vectorizing a tree of floating-point multiplies,72; may look profitable; but both are not because this eliminates generation73; of floating-point FMAs that would be more profitable.74 75define double @hr_or_mul() {76; SSE4-LABEL: @hr_or_mul(77; SSE4-NEXT: [[CVT0:%.*]] = uitofp i16 3 to double78; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 079; SSE4-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> poison, <4 x i32> zeroinitializer80; SSE4-NEXT: [[TMP3:%.*]] = fmul fast <4 x double> <double 7.000000e+00, double -4.300000e+01, double 2.200000e-02, double 9.500000e+00>, [[TMP2]]81; SSE4-NEXT: [[TMP4:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP3]])82; SSE4-NEXT: [[OP_RDX:%.*]] = fadd fast double [[TMP4]], [[CVT0]]83; SSE4-NEXT: ret double [[OP_RDX]]84;85; AVX-LABEL: @hr_or_mul(86; AVX-NEXT: [[CVT0:%.*]] = uitofp i16 3 to double87; AVX-NEXT: [[TMP4:%.*]] = fmul fast double 7.000000e+00, [[CVT0]]88; AVX-NEXT: [[ADD3:%.*]] = fadd fast double [[TMP4]], [[CVT0]]89; AVX-NEXT: [[MUL1:%.*]] = fmul fast double -4.300000e+01, [[CVT0]]90; AVX-NEXT: [[ADD1:%.*]] = fadd fast double [[MUL1]], [[ADD3]]91; AVX-NEXT: [[MUL2:%.*]] = fmul fast double 2.200000e-02, [[CVT0]]92; AVX-NEXT: [[ADD2:%.*]] = fadd fast double [[MUL2]], [[ADD1]]93; AVX-NEXT: [[MUL3:%.*]] = fmul fast double 9.500000e+00, [[CVT0]]94; AVX-NEXT: [[ADD4:%.*]] = fadd fast double [[MUL3]], [[ADD2]]95; AVX-NEXT: ret double [[ADD4]]96;97; AVX2-LABEL: @hr_or_mul(98; AVX2-NEXT: [[CVT0:%.*]] = uitofp i16 3 to double99; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 0100; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> poison, <4 x i32> zeroinitializer101; AVX2-NEXT: [[TMP3:%.*]] = fmul fast <4 x double> <double 7.000000e+00, double -4.300000e+01, double 2.200000e-02, double 9.500000e+00>, [[TMP2]]102; AVX2-NEXT: [[TMP4:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP3]])103; AVX2-NEXT: [[OP_RDX:%.*]] = fadd fast double [[TMP4]], [[CVT0]]104; AVX2-NEXT: ret double [[OP_RDX]]105;106 %cvt0 = uitofp i16 3 to double107 %mul0 = fmul fast double 7.000000e+00, %cvt0108 %add0 = fadd fast double %mul0, %cvt0109 %mul1 = fmul fast double -4.300000e+01, %cvt0110 %add1 = fadd fast double %mul1, %add0111 %mul2 = fmul fast double 2.200000e-02, %cvt0112 %add2 = fadd fast double %mul2, %add1113 %mul3 = fmul fast double 9.500000e+00, %cvt0114 %add3 = fadd fast double %mul3, %add2115 ret double %add3116}117