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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-sie-ps5 -mcpu=znver2 < %s | FileCheck %s3 4define i1 @test(ptr %0, ptr %1, <2 x float> %2, <2 x float> %3, <2 x float> %4) {5; CHECK-LABEL: define i1 @test(6; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], <2 x float> [[TMP3:%.*]], <2 x float> [[TMP4:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[TMP1]], align 48; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP0]], align 49; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP0]], align 410; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP4]], i64 011; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[TMP6]], i32 012; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x float> [[TMP10]], float [[TMP7]], i32 113; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> [[TMP11]], float [[TMP8]], i32 614; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x float> [[TMP12]], <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 6, i32 6>15; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP3]], <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 poison>16; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[TMP9]], i32 717; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <8 x float> [[TMP13]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>18; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <8 x float> [[TMP15]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>19; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x float> [[TMP16]], <16 x float> [[TMP23]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>20; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <8 x float> [[TMP14]], <8 x float> [[TMP12]], <16 x i32> <i32 8, i32 9, i32 9, i32 9, i32 9, i32 9, i32 14, i32 14, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison>21; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP9]], i32 1522; CHECK-NEXT: [[TMP20:%.*]] = fmul <16 x float> [[TMP18]], [[TMP17]]23; CHECK-NEXT: [[TMP21:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> [[TMP20]])24; CHECK-NEXT: [[TMP22:%.*]] = call float @foo(float [[TMP21]])25; CHECK-NEXT: ret i1 false26;27 %6 = load float, ptr %1, align 428 %7 = load float, ptr %0, align 429 %8 = fmul float %6, %630 %9 = fmul float %7, %731 %10 = fmul float %7, %732 %11 = fmul float %7, %733 %12 = fmul float %7, %734 %13 = fmul float %7, %735 %14 = load float, ptr %0, align 436 %15 = fmul float %14, %1437 %16 = fmul float %14, %1438 %17 = extractelement <2 x float> %2, i64 039 %18 = extractelement <2 x float> %2, i64 040 %19 = fmul float %17, %1741 %20 = fmul float %18, %1842 %21 = extractelement <2 x float> %3, i64 043 %22 = extractelement <2 x float> %2, i64 044 %23 = fmul float %21, %2145 %24 = fmul float %22, %2246 %25 = extractelement <2 x float> %2, i64 047 %26 = extractelement <2 x float> %2, i64 048 %27 = fmul float %25, %2549 %28 = fmul float %26, %2650 %29 = extractelement <2 x float> %2, i64 051 %30 = extractelement <2 x float> %4, i64 052 %31 = fmul float %29, %2953 %32 = fmul float %30, %3054 %33 = fadd reassoc nsz float %8, %955 %34 = fadd reassoc nsz float %33, %1056 %35 = fadd reassoc nsz float %34, %1157 %36 = fadd reassoc nsz float %35, %1258 %37 = fadd reassoc nsz float %36, %1359 %38 = fadd reassoc nsz float %37, %1560 %39 = fadd reassoc nsz float %38, %1661 %40 = fadd reassoc nsz float %39, %1962 %41 = fadd reassoc nsz float %40, %2063 %42 = fadd reassoc nsz float %41, %2364 %43 = fadd reassoc nsz float %42, %2465 %44 = fadd reassoc nsz float %43, %2766 %45 = fadd reassoc nsz float %44, %2867 %46 = fadd reassoc nsz float %45, %3168 %47 = fadd reassoc nsz float %46, %3269 %48 = call float @foo(float %47)70 ret i1 false71}72 73declare float @foo(float)74