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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s3 4define void @test(ptr %p) {5; CHECK-LABEL: define void @test(6; CHECK-SAME: ptr [[P:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[ARRAYIDX7_US_I_841:%.*]] = getelementptr i8, ptr [[P]], i64 369; CHECK-NEXT: [[ARRAYIDX7_US_I_1261:%.*]] = getelementptr i8, ptr [[P]], i64 5210; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 411; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX7_US_I_1261]], align 412; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>13; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>14; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> [[TMP19]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>15; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>16; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[ARRAYIDX7_US_I_841]], align 417; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>18; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>19; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <12 x i32> [[TMP6]], <12 x i32> [[TMP20]], <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>20; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>21; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>22; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 18, i32 poison, i32 poison, i32 poison, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>23; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i32> [[TMP10]], i32 [[TMP0]], i32 624; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x i32> [[TMP11]], <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 6, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>25; CHECK-NEXT: [[TMP13:%.*]] = add <16 x i32> [[TMP3]], [[TMP12]]26; CHECK-NEXT: [[TMP14:%.*]] = srem <16 x i32> [[TMP13]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>27; CHECK-NEXT: [[TMP15:%.*]] = or <12 x i32> [[TMP7]], zeroinitializer28; CHECK-NEXT: [[TMP16:%.*]] = srem <12 x i32> [[TMP15]], <i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>29; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER_US_I:.*]]30; CHECK: [[FOR_COND1_PREHEADER_US_I]]:31; CHECK-NEXT: [[A_PROMOTED253537_US_I:%.*]] = phi i32 [ [[OP_RDX8:%.*]], %[[FOR_COND1_PREHEADER_US_I]] ], [ 0, %[[ENTRY]] ]32; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP14]])33; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.v12i32(<12 x i32> [[TMP16]])34; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP18]], [[TMP17]]35; CHECK-NEXT: [[OP_RDX8]] = add i32 [[OP_RDX]], 036; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER_US_I]]37;38entry:39 %arrayidx7.us.i.841 = getelementptr i8, ptr %p, i64 3640 %arrayidx7.us.i.946 = getelementptr i8, ptr %p, i64 4041 %arrayidx7.us.i.1051 = getelementptr i8, ptr %p, i64 4442 %arrayidx7.us.i.1156 = getelementptr i8, ptr %p, i64 4843 %arrayidx7.us.i.1261 = getelementptr i8, ptr %p, i64 5244 %arrayidx7.us.i.1366 = getelementptr i8, ptr %p, i64 5645 %arrayidx7.us.i.1471 = getelementptr i8, ptr %p, i64 6046 %arrayidx7.us.i.1576 = getelementptr i8, ptr %p, i64 6447 %add8.us.i.1.4 = add i32 0, 048 %rem.us.i.1.4 = srem i32 %add8.us.i.1.4, 149 %add8.us.i.1.5 = add i32 0, 050 %rem.us.i.1.5 = srem i32 %add8.us.i.1.5, 151 %invariant.op91 = add i32 %rem.us.i.1.4, %rem.us.i.1.552 %add8.us.i.1.6 = add i32 0, 053 %rem.us.i.1.6 = srem i32 %add8.us.i.1.6, 154 %invariant.op92 = add i32 %invariant.op91, %rem.us.i.1.655 %0 = load i32, ptr %arrayidx7.us.i.841, align 456 %1 = load i32, ptr %arrayidx7.us.i.946, align 457 %2 = load i32, ptr %arrayidx7.us.i.1051, align 458 %3 = load i32, ptr %arrayidx7.us.i.1156, align 459 %4 = load i32, ptr %arrayidx7.us.i.1261, align 460 %5 = load i32, ptr %arrayidx7.us.i.1366, align 461 %add8.us.i.7.6 = or i32 %5, 062 %rem.us.i.7.6 = srem i32 %add8.us.i.7.6, 163 %6 = load i32, ptr %arrayidx7.us.i.1471, align 464 %add8.us.i.7.7 = or i32 %6, 065 %rem.us.i.7.7 = srem i32 %add8.us.i.7.7, 166 %invariant.op165 = add i32 %rem.us.i.7.6, %rem.us.i.7.767 %7 = load i32, ptr %arrayidx7.us.i.1576, align 468 %add8.us.i.7.8 = or i32 %7, 069 %rem.us.i.7.8 = srem i32 %add8.us.i.7.8, 170 %invariant.op166 = add i32 %invariant.op165, %rem.us.i.7.871 %add8.us.i.8 = or i32 %0, 072 %rem.us.i.8 = srem i32 %add8.us.i.8, 173 %invariant.op167 = add i32 %invariant.op166, %rem.us.i.874 %add8.us.i.8.1 = or i32 %1, 075 %rem.us.i.8.1 = srem i32 %add8.us.i.8.1, 176 %invariant.op168 = add i32 %invariant.op167, %rem.us.i.8.177 %add8.us.i.8.2 = or i32 %2, 078 %rem.us.i.8.2 = srem i32 %add8.us.i.8.2, 179 %invariant.op169 = add i32 %invariant.op168, %rem.us.i.8.280 %add8.us.i.8.3 = or i32 %3, 081 %rem.us.i.8.3 = srem i32 %add8.us.i.8.3, 182 %invariant.op170 = add i32 %invariant.op169, %rem.us.i.8.383 %add8.us.i.8.4 = or i32 %4, 084 %rem.us.i.8.4 = srem i32 %add8.us.i.8.4, 185 %invariant.op171 = add i32 %invariant.op170, %rem.us.i.8.486 %add8.us.i.8.5 = or i32 %5, 087 %rem.us.i.8.5 = srem i32 %add8.us.i.8.5, 188 %invariant.op172 = add i32 %invariant.op171, %rem.us.i.8.589 %add8.us.i.8.6 = or i32 %6, 090 %rem.us.i.8.6 = srem i32 %add8.us.i.8.6, 091 %invariant.op173 = add i32 %invariant.op172, %rem.us.i.8.692 %add8.us.i.8.7 = or i32 %7, 093 %rem.us.i.8.7 = srem i32 %add8.us.i.8.7, 094 %invariant.op174 = add i32 %invariant.op173, %rem.us.i.8.795 %invariant.op181 = add i32 %invariant.op174, 096 %invariant.op182 = add i32 %invariant.op181, 097 %invariant.op183 = add i32 %invariant.op182, 098 %invariant.op184 = add i32 %invariant.op183, 099 %invariant.op185 = add i32 %invariant.op184, 0100 %invariant.op186 = add i32 %invariant.op185, 0101 %invariant.op187 = add i32 %invariant.op186, 0102 %invariant.op188 = add i32 %invariant.op187, 0103 %add8.us.i.11.1 = or i32 %4, 0104 %rem.us.i.11.1 = srem i32 %add8.us.i.11.1, 1105 %invariant.op189 = add i32 %invariant.op188, %rem.us.i.11.1106 %add8.us.i.11.2 = add i32 0, 0107 %rem.us.i.11.2 = srem i32 %add8.us.i.11.2, 1108 %invariant.op190 = add i32 %invariant.op189, %rem.us.i.11.2109 %add8.us.i.11.3 = add i32 %6, %2110 %rem.us.i.11.3 = srem i32 %add8.us.i.11.3, 1111 %invariant.op191 = add i32 %invariant.op190, %rem.us.i.11.3112 %add8.us.i.11.4 = add i32 %7, %2113 %rem.us.i.11.4 = srem i32 %add8.us.i.11.4, 1114 %invariant.op192 = add i32 %invariant.op191, %rem.us.i.11.4115 %8 = load i32, ptr %p, align 4116 %add8.us.i.12 = add i32 %4, %8117 %rem.us.i.12 = srem i32 %add8.us.i.12, 1118 %invariant.op193 = add i32 %invariant.op192, %rem.us.i.12119 %add8.us.i.12.1 = add i32 %5, %8120 %rem.us.i.12.1 = srem i32 %add8.us.i.12.1, 1121 %invariant.op194 = add i32 %invariant.op193, %rem.us.i.12.1122 %add8.us.i.12.2 = add i32 0, 0123 %rem.us.i.12.2 = srem i32 %add8.us.i.12.2, 1124 %invariant.op195 = add i32 %invariant.op194, %rem.us.i.12.2125 %add8.us.i.12.3 = add i32 0, 0126 %rem.us.i.12.3 = srem i32 %add8.us.i.12.3, 1127 %invariant.op196 = add i32 %invariant.op195, %rem.us.i.12.3128 %add8.us.i.13 = add i32 0, 0129 %rem.us.i.13 = srem i32 %add8.us.i.13, 0130 %invariant.op197 = add i32 %invariant.op196, %rem.us.i.13131 %add8.us.i.13.1 = add i32 0, 0132 %rem.us.i.13.1 = srem i32 %add8.us.i.13.1, 0133 %invariant.op198 = add i32 %invariant.op197, %rem.us.i.13.1134 %add8.us.i.13.2 = add i32 0, 0135 %rem.us.i.13.2 = srem i32 %add8.us.i.13.2, 1136 %invariant.op199 = add i32 %invariant.op198, %rem.us.i.13.2137 %add8.us.i.14 = add i32 0, 0138 %rem.us.i.14 = srem i32 %add8.us.i.14, 1139 %invariant.op200 = add i32 %invariant.op199, %rem.us.i.14140 %add8.us.i.14.1 = add i32 0, 0141 %rem.us.i.14.1 = srem i32 %add8.us.i.14.1, 1142 %invariant.op201 = add i32 %invariant.op200, %rem.us.i.14.1143 %add8.us.i.15 = add i32 0, 0144 %rem.us.i.15 = srem i32 %add8.us.i.15, 1145 %invariant.op202 = add i32 %invariant.op201, %rem.us.i.15146 br label %for.cond1.preheader.us.i147 148for.cond1.preheader.us.i:149 %a.promoted253537.us.i = phi i32 [ %add9.us.i.15.reass, %for.cond1.preheader.us.i ], [ 0, %entry ]150 %add9.us.i.15.reass = add i32 %invariant.op92, %invariant.op202151 br label %for.cond1.preheader.us.i152}153 154