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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s3 4define i32 @alt_cmp(i16 %call46) {5; CHECK-LABEL: @alt_cmp(6; CHECK-NEXT: entry:7; CHECK-NEXT: [[CALL47:%.*]] = tail call i16 null(i16 0)8; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL46:%.*]], i32 19; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL47]], i32 110; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]11; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]12; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>13; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])14; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i1615; CHECK-NEXT: [[OP_RDX:%.*]] = or i16 [[TMP6]], 016; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[OP_RDX]] to i3217; CHECK-NEXT: ret i32 [[EXT]]18;19entry:20 %0 = icmp ult i16 0, 021 %cond40 = zext i1 %0 to i1622 %add41 = or i16 0, %cond4023 %call47 = tail call i16 null(i16 0)24 %.not299 = icmp ugt i16 %call46, %call4725 %cond60 = zext i1 %.not299 to i1626 %add61 = or i16 %add41, %cond6027 %1 = icmp ugt i16 0, 028 %cond76 = zext i1 %1 to i1629 %add77 = or i16 %add61, %cond7630 %2 = icmp ult i16 0, 031 %cond144 = zext i1 %2 to i1632 %add145 = or i16 %add77, %cond14433 %ext = zext i16 %add145 to i3234 ret i32 %ext35}36