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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=X86 %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=AARCH64 %}4 5define <2 x i32> @test(i32 %arg) {6; X86-LABEL: define <2 x i32> @test(7; X86-SAME: i32 [[ARG:%.*]]) {8; X86-NEXT: bb:9; X86-NEXT: [[OR:%.*]] = or i32 [[ARG]], 010; X86-NEXT: [[MUL:%.*]] = mul i32 0, 111; X86-NEXT: [[MUL1:%.*]] = mul i32 [[OR]], [[MUL]]12; X86-NEXT: [[CMP:%.*]] = icmp ugt i32 0, [[MUL1]]13; X86-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[OR]], i32 014; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[MUL]], i32 115; X86-NEXT: ret <2 x i32> [[TMP1]]16;17; AARCH64-LABEL: define <2 x i32> @test(18; AARCH64-SAME: i32 [[ARG:%.*]]) {19; AARCH64-NEXT: bb:20; AARCH64-NEXT: [[TMP2:%.*]] = or i32 [[ARG]], 021; AARCH64-NEXT: [[TMP3:%.*]] = mul i32 0, 122; AARCH64-NEXT: [[MUL1:%.*]] = mul i32 [[TMP2]], [[TMP3]]23; AARCH64-NEXT: [[CMP:%.*]] = icmp ugt i32 0, [[MUL1]]24; AARCH64-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i32 025; AARCH64-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[TMP3]], i32 126; AARCH64-NEXT: ret <2 x i32> [[TMP1]]27;28bb:29 %or = or i32 %arg, 030 %mul = mul i32 0, 131 %mul1 = mul i32 %or, %mul32 %cmp = icmp ugt i32 0, %mul133 %0 = insertelement <2 x i32> poison, i32 %or, i32 034 %1 = insertelement <2 x i32> %0, i32 %mul, i32 135 ret <2 x i32> %136}37 38