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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-pc-windows-msvc19.34.0 < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5define void @test(ptr %0, i8 %1, i1 %cmp12.i) {6; CHECK-LABEL: define void @test(7; CHECK-SAME: ptr [[TMP0:%.*]], i8 [[TMP1:%.*]], i1 [[CMP12_I:%.*]]) {8; CHECK-NEXT: entry:9; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]], i32 010; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <8 x i32> zeroinitializer11; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]], i32 012; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer13; CHECK-NEXT: br label [[PRE:%.*]]14; CHECK: pre:15; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP5]], <8 x i8> splat (i8 1))16; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i8> [[TMP6]], splat (i8 1)17; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x i8> [[TMP9]], <8 x i8> [[TMP5]]18; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP0]], align 119; CHECK-NEXT: br label [[PRE]]20;21entry:22 %idx11 = getelementptr i8, ptr %0, i64 123 %idx22 = getelementptr i8, ptr %0, i64 224 %idx33 = getelementptr i8, ptr %0, i64 325 %idx44 = getelementptr i8, ptr %0, i64 426 %idx55 = getelementptr i8, ptr %0, i64 527 %idx66 = getelementptr i8, ptr %0, i64 628 %idx77 = getelementptr i8, ptr %0, i64 729 br label %pre30 31pre:32 %conv.i = zext i8 %1 to i3233 %2 = tail call i32 @llvm.umax.i32(i32 %conv.i, i32 1)34 %.sroa.speculated.i = add i32 %2, 135 %intensity.0.i = select i1 %cmp12.i, i32 %.sroa.speculated.i, i32 %conv.i36 %conv14.i = trunc i32 %intensity.0.i to i837 store i8 %conv14.i, ptr %0, align 138 %conv.i.1 = zext i8 %1 to i3239 %3 = tail call i32 @llvm.umax.i32(i32 %conv.i.1, i32 1)40 %ss1 = add i32 %3, 141 %ii1 = select i1 %cmp12.i, i32 %ss1, i32 %conv.i.142 %conv14.i.1 = trunc i32 %ii1 to i843 store i8 %conv14.i.1, ptr %idx11, align 144 %conv.i.2 = zext i8 %1 to i3245 %4 = tail call i32 @llvm.umax.i32(i32 %conv.i.2, i32 1)46 %ss2 = add i32 %4, 147 %ii2 = select i1 %cmp12.i, i32 %ss2, i32 %conv.i.248 %conv14.i.2 = trunc i32 %ii2 to i849 store i8 %conv14.i.2, ptr %idx22, align 150 %conv.i.3 = zext i8 %1 to i3251 %5 = tail call i32 @llvm.umax.i32(i32 %conv.i.3, i32 1)52 %ss3 = add i32 %5, 153 %ii3 = select i1 %cmp12.i, i32 %ss3, i32 %conv.i.354 %conv14.i.3 = trunc i32 %ii3 to i855 store i8 %conv14.i.3, ptr %idx33, align 156 %conv.i.4 = zext i8 %1 to i3257 %6 = tail call i32 @llvm.umax.i32(i32 %conv.i.4, i32 1)58 %ss4 = add i32 %6, 159 %ii4 = select i1 %cmp12.i, i32 %ss4, i32 %conv.i.460 %conv14.i.4 = trunc i32 %ii4 to i861 store i8 %conv14.i.4, ptr %idx44, align 162 %conv.i.5 = zext i8 %1 to i3263 %7 = tail call i32 @llvm.umax.i32(i32 %conv.i.5, i32 1)64 %ss5 = add i32 %7, 165 %ii5 = select i1 %cmp12.i, i32 %ss5, i32 %conv.i.566 %conv14.i.5 = trunc i32 %ii5 to i867 store i8 %conv14.i.5, ptr %idx55, align 168 %conv.i.6 = zext i8 %1 to i3269 %8 = tail call i32 @llvm.umax.i32(i32 %conv.i.6, i32 1)70 %ss6 = add i32 %8, 171 %ii6 = select i1 %cmp12.i, i32 %ss6, i32 %conv.i.672 %conv14.i.6 = trunc i32 %ii6 to i873 store i8 %conv14.i.6, ptr %idx66, align 174 %conv.i.7 = zext i8 %1 to i3275 %9 = tail call i32 @llvm.umax.i32(i32 %conv.i.7, i32 1)76 %ss7 = add i32 %9, 177 %ii7 = select i1 %cmp12.i, i32 %ss7, i32 %conv.i.778 %conv14.i.7 = trunc i32 %ii7 to i879 store i8 %conv14.i.7, ptr %idx77, align 180 br label %pre81}82