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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux < %s | FileCheck %s %}4 5define void @test(ptr %top) {6; CHECK-LABEL: define void @test(7; CHECK-SAME: ptr [[TOP:%.*]]) {8; CHECK-NEXT: entry:9; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TOP]], align 110; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[TMP0]], zeroinitializer11; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 212; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i3213; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i814; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[TMP4]], i32 315; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i8> [[TMP1]], [[TMP5]]16; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i8> [[TMP6]], zeroinitializer17; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i8> [[TMP7]], splat (i8 2)18; CHECK-NEXT: br label [[FOR_COND_I:%.*]]19; CHECK: for.cond.i:20; CHECK-NEXT: store <4 x i8> [[TMP8]], ptr null, align 121; CHECK-NEXT: br label [[FOR_COND_I]]22;23entry:24 %0 = load i8, ptr %top, align 125 %conv2.i = zext i8 %0 to i3226 %mul.i = mul i32 %conv2.i, 027 %add.i = or i32 %mul.i, 028 %arrayidx3.i = getelementptr i8, ptr %top, i64 129 %1 = load i8, ptr %arrayidx3.i, align 130 %conv4.i = zext i8 %1 to i3231 %add5.i = or i32 %add.i, 032 %shr.i = lshr i32 %add5.i, 233 %conv7.i = trunc i32 %shr.i to i834 %mul12.i = mul i32 %conv4.i, 035 %arrayidx14.i = getelementptr i8, ptr %top, i64 236 %2 = load i8, ptr %arrayidx14.i, align 137 %conv15.i = zext i8 %2 to i3238 %add16.i = or i32 %mul12.i, 039 %add17.i = or i32 %add16.i, 040 %shr18.i = lshr i32 %add17.i, 241 %conv19.i = trunc i32 %shr18.i to i842 %mul25.i = mul i32 %conv15.i, 043 %arrayidx27.i = getelementptr i8, ptr %top, i64 344 %3 = load i8, ptr %arrayidx27.i, align 145 %conv28.i = zext i8 %3 to i3246 %add29.i = or i32 %mul25.i, 047 %add30.i = or i32 %add29.i, 048 %shr31.i = lshr i32 %add30.i, 249 %conv32.i = trunc i32 %shr31.i to i850 %mul38.i = mul i32 %conv28.i, 051 %add39.i = or i32 %mul38.i, %conv15.i52 %add42.i = or i32 %add39.i, 053 %shr44.i = lshr i32 %add42.i, 254 %conv45.i = trunc i32 %shr44.i to i855 br label %for.cond.i56 57for.cond.i:58 store i8 %conv7.i, ptr null, align 159 %vals.sroa.5.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 160 store i8 %conv19.i, ptr %vals.sroa.5.0.add.ptr.sroa_idx.i, align 161 %vals.sroa.7.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 262 store i8 %conv32.i, ptr %vals.sroa.7.0.add.ptr.sroa_idx.i, align 163 %vals.sroa.9.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 364 store i8 %conv45.i, ptr %vals.sroa.9.0.add.ptr.sroa_idx.i, align 165 br label %for.cond.i66}67