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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5@e = global i8 06@c = global i16 07@d = global i32 08 9define i8 @test() {10; CHECK-LABEL: define i8 @test() {11; CHECK-NEXT: entry:12; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @e, align 113; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i3214; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @c, align 215; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[TMP1]] to i3216; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[CONV]], 3276917; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i32 018; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> zeroinitializer19; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP3]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 32769>20; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> poison, i32 [[CONV1]], i32 021; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <8 x i32> zeroinitializer22; CHECK-NEXT: [[TMP8:%.*]] = add nsw <8 x i32> [[TMP4]], [[TMP7]]23; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP8]])24; CHECK-NEXT: [[CONV4_30:%.*]] = trunc i32 [[TMP11]] to i825; CHECK-NEXT: [[XOR_31:%.*]] = and i32 [[TMP13]], -226; CHECK-NEXT: store i32 [[XOR_31]], ptr @d, align 427; CHECK-NEXT: ret i8 [[CONV4_30]]28;29entry:30 %0 = load i8, ptr @e, align 131 %conv = sext i8 %0 to i3232 %1 = load i16, ptr @c, align 233 %conv1 = zext i16 %1 to i3234 %or.16 = or i32 %conv, 135 %add.16 = add nsw i32 %or.16, %conv136 %or.18 = or i32 %conv, 137 %add.18 = add nsw i32 %or.18, %conv138 %conv4.181 = or i32 %add.16, %add.1839 %or.20 = or i32 %conv, 140 %add.20 = add nsw i32 %or.20, %conv141 %conv4.202 = or i32 %conv4.181, %add.2042 %or.22 = or i32 %conv, 143 %add.22 = add nsw i32 %or.22, %conv144 %conv4.223 = or i32 %conv4.202, %add.2245 %or.24 = or i32 %conv, 146 %add.24 = add nsw i32 %or.24, %conv147 %conv4.244 = or i32 %conv4.223, %add.2448 %or.26 = or i32 %conv, 149 %add.26 = add nsw i32 %or.26, %conv150 %conv4.265 = or i32 %conv4.244, %add.2651 %or.28 = or i32 %conv, 152 %add.28 = add nsw i32 %or.28, %conv153 %conv4.286 = or i32 %conv4.265, %add.2854 %or.30 = or i32 %conv, 3276955 %add.30 = add nsw i32 %or.30, %conv156 %conv4.307 = or i32 %conv4.286, %add.3057 %conv4.30 = trunc i32 %conv4.307 to i858 %xor.31 = and i32 %or.30, -259 store i32 %xor.31, ptr @d, align 460 ret i8 %conv4.3061}62