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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: %if x86-registered-target %{ opt -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -passes=slp-vectorizer -S -o - -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5%struct.sw = type { float, float, float, float }6 7define { <2 x float>, <2 x float> } @foo(ptr %v) {8; CHECK-LABEL: @foo(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr undef, align 411; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr undef, align 412; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[V:%.*]], align 1613; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>14; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float undef>, float [[TMP0]], i32 115; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[TMP1]], i32 216; CHECK-NEXT: [[TMP6:%.*]] = fmul <4 x float> [[SHUFFLE]], [[TMP5]]17; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP6]], undef18; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[TMP7]], undef19; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x float> [[TMP8]], undef20; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> poison, <2 x i32> <i32 1, i32 0>21; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> poison, <2 x i32> <i32 2, i32 3>22; CHECK-NEXT: [[INS1:%.*]] = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> [[TMP10]], 023; CHECK-NEXT: [[INS2:%.*]] = insertvalue { <2 x float>, <2 x float> } [[INS1]], <2 x float> [[TMP11]], 124; CHECK-NEXT: ret { <2 x float>, <2 x float> } [[INS2]]25;26entry:27 %0 = load float, ptr undef, align 428 %1 = load float, ptr %v, align 1629 %y = getelementptr inbounds %struct.sw, ptr %v, i64 0, i32 130 %2 = load float, ptr %y, align 431 %mul3 = fmul float %0, %232 %add = fadd float undef, %mul333 %add6 = fadd float %add, undef34 %add9 = fadd float %add6, undef35 %mul12 = fmul float %1, undef36 %add16 = fadd float %mul12, undef37 %add20 = fadd float undef, %add1638 %add24 = fadd float undef, %add2039 %3 = load float, ptr undef, align 440 %mul27 = fmul float %1, %341 %add31 = fadd float %mul27, undef42 %add35 = fadd float undef, %add3143 %add39 = fadd float undef, %add3544 %mul45 = fmul float %2, undef45 %add46 = fadd float undef, %mul4546 %add50 = fadd float undef, %add4647 %add54 = fadd float undef, %add5048 %vec1 = insertelement <2 x float> undef, float %add9, i32 049 %vec2 = insertelement <2 x float> %vec1, float %add24, i32 150 %vec3 = insertelement <2 x float> undef, float %add39, i32 051 %vec4 = insertelement <2 x float> %vec3, float %add54, i32 152 %ins1 = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> %vec2, 053 %ins2 = insertvalue { <2 x float>, <2 x float> } %ins1, <2 x float> %vec4, 154 ret { <2 x float>, <2 x float> } %ins255}56