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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-9 < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu -slp-threshold=-9 < %s | FileCheck %s %}4 5define void @t(i64 %v) {6; CHECK-LABEL: define void @t(7; CHECK-SAME: i64 [[V:%.*]]) {8; CHECK-NEXT: entry:9; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[V]] to i1610; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 011; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer12; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i16> [[TMP2]], <i16 2, i16 3, i16 6, i16 5>13; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP3]])14; CHECK-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i3215; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 6553516; CHECK-NEXT: store i32 [[TMP6]], ptr null, align 417; CHECK-NEXT: ret void18;19entry:20 %conv12.1.i = trunc i64 %v to i3221 %mul.i.1.i = mul i32 %conv12.1.i, 222 %conv12.i = trunc i64 %v to i3223 %mul.i.i = mul i32 %conv12.i, 324 %conv14104.i = or i32 %mul.i.1.i, %mul.i.i25 %conv12.1.i.1 = trunc i64 %v to i3226 %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 627 %conv12.i.1 = trunc i64 %v to i3228 %mul.i.i.1 = mul i32 %conv12.i.1, 529 %conv14104.i.1 = or i32 %mul.i.1.i.1, %mul.i.i.130 %0 = or i32 %conv14104.i, %conv14104.i.131 %1 = and i32 %0, 6553532 store i32 %1, ptr null, align 433 ret void34}35