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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5define void @test() {6; CHECK-LABEL: define void @test() {7; CHECK-NEXT: entry:8; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr null, align 29; CHECK-NEXT: [[TMP2:%.*]] = and i32 0, 010; CHECK-NEXT: [[TMP3:%.*]] = select i1 false, i32 0, i32 011; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i8> zeroinitializer, zeroinitializer12; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i8> [[TMP8]] to <4 x i1>13; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i1> [[TMP9]], zeroinitializer14; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer15; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP13]])16; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 0, [[TMP14]]17; CHECK-NEXT: store i32 [[OP_RDX]], ptr null, align 418; CHECK-NEXT: ret void19;20entry:21 %0 = load i16, ptr null, align 222 %1 = and i8 0, 123 %2 = and i32 0, 024 %3 = select i1 false, i32 0, i32 025 %i2 = sext i8 %1 to i3226 %i3 = or i8 %1, 027 %i4 = sext i8 %i3 to i3228 %i5 = or i32 0, %i229 %b1 = icmp eq i32 %i4, %i530 %a1 = select i1 %b1, i32 0, i32 031 %4 = and i32 %a1, 032 %s1 = and i32 %4, 033 %i8 = sext i8 %1 to i3234 %i9 = or i8 %1, 035 %i10 = sext i8 %i9 to i3236 %i11 = or i32 0, %i837 %b2 = icmp eq i32 %i10, %i1138 %a2 = select i1 %b2, i32 0, i32 039 %5 = and i32 %a2, 040 %s2 = and i32 %5, %s141 %i14 = sext i8 %1 to i3242 %i15 = or i8 %1, 043 %i16 = sext i8 %i15 to i3244 %i17 = or i32 0, %i1445 %b3 = icmp eq i32 %i16, %i1746 %a3 = select i1 %b3, i32 %i14, i32 047 %6 = and i32 %a3, 048 %s3 = and i32 %6, %s249 %i20 = sext i8 0 to i3250 %i21 = or i8 %1, 051 %i22 = sext i8 %i21 to i3252 %i23 = or i32 0, %i2053 %b4 = icmp eq i32 %i22, %i2354 %a4 = select i1 %b4, i32 0, i32 055 %7 = and i32 %a4, 056 %s4 = and i32 %7, %s357 store i32 %s4, ptr null, align 458 ret void59}60