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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s -slp-threshold=-10 | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux < %s -slp-threshold=-10 | FileCheck %s %}4 5define i64 @src(i32 %a) {6; CHECK-LABEL: define i64 @src(7; CHECK-SAME: i32 [[A:%.*]]) {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: [[TMP17:%.*]] = sext i32 [[A]] to i6410; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 011; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer12; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>13; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], splat (i64 4294967297)14; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i64> [[TMP4]], splat (i64 1)15; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP6]])16; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP4]])17; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP16]], i32 018; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> [[TMP8]], i64 [[TMP18]], i32 119; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> <i64 poison, i64 4294967297>, i64 [[TMP17]], i32 020; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP9]], [[TMP10]]21; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP11]], i32 022; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[TMP11]], i32 123; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP12]], [[TMP13]]24; CHECK-NEXT: ret i64 [[TMP21]]25;26entry:27 %0 = sext i32 %a to i6428 %1 = add nsw i64 %0, 429496729729 %2 = sext i32 %a to i6430 %3 = add nsw i64 %2, 429496729731 %4 = add i64 %3, %132 %5 = and i64 %3, 133 %6 = add i64 %4, %534 %7 = sext i32 %a to i6435 %8 = add nsw i64 %7, 429496729736 %9 = add i64 %8, %637 %10 = and i64 %8, 138 %11 = add i64 %9, %1039 %12 = sext i32 %a to i6440 %13 = add nsw i64 %12, 429496729741 %14 = add i64 %13, %1142 %15 = and i64 %13, 143 %16 = add i64 %14, %1544 %17 = sext i32 %a to i6445 %18 = add nsw i64 %17, 429496729746 %19 = add i64 %18, %1647 %20 = and i64 %18, 148 %21 = add i64 %19, %2049 ret i64 %2150}51