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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: %if x86-registered-target %{ opt < %s -passes=slp-vectorizer -slp-threshold=-1000 -mtriple=x86_64 -S | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt < %s -passes=slp-vectorizer -slp-threshold=-1000 -mtriple=aarch64-unknown-linux-gnu -S | FileCheck %s %}4 5; The inputs to vector phi should remain undef.6 7define i32 @phi3UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {8; CHECK-LABEL: @phi3UndefInput(9; CHECK-NEXT: entry:10; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]11; CHECK: bb2:12; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 013; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 114; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 215; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 316; CHECK-NEXT: br label [[BB3]]17; CHECK: bb3:18; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 undef, i8 undef, i8 undef>, [[ENTRY:%.*]] ]19; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])20; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3221; CHECK-NEXT: ret i32 [[TMP6]]22;23entry:24 br i1 %cond, label %bb2, label %bb325 26bb2:27 br label %bb328 29bb3:30 %phi0 = phi i8 [ %arg0, %bb2 ], [ 0, %entry ]31 %phi1 = phi i8 [ %arg1, %bb2 ], [ undef, %entry ]32 %phi2 = phi i8 [ %arg2, %bb2 ], [ undef, %entry ]33 %phi3 = phi i8 [ %arg3, %bb2 ], [ undef, %entry ]34 %zext0 = zext i8 %phi0 to i3235 %zext1 = zext i8 %phi1 to i3236 %zext2 = zext i8 %phi2 to i3237 %zext3 = zext i8 %phi3 to i3238 %or1 = or i32 %zext0, %zext139 %or2 = or i32 %or1, %zext240 %or3 = or i32 %or2, %zext341 ret i32 %or342}43 44define i32 @phi2UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {45; CHECK-LABEL: @phi2UndefInput(46; CHECK-NEXT: entry:47; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]48; CHECK: bb2:49; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 050; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 151; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 252; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 353; CHECK-NEXT: br label [[BB3]]54; CHECK: bb3:55; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 undef, i8 undef>, [[ENTRY:%.*]] ]56; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])57; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3258; CHECK-NEXT: ret i32 [[TMP6]]59;60entry:61 br i1 %cond, label %bb2, label %bb362 63bb2:64 br label %bb365 66bb3:67 %phi0 = phi i8 [ %arg0, %bb2 ], [ 0, %entry ]68 %phi1 = phi i8 [ %arg1, %bb2 ], [ 0, %entry ]69 %phi2 = phi i8 [ %arg2, %bb2 ], [ undef, %entry ]70 %phi3 = phi i8 [ %arg3, %bb2 ], [ undef, %entry ]71 %zext0 = zext i8 %phi0 to i3272 %zext1 = zext i8 %phi1 to i3273 %zext2 = zext i8 %phi2 to i3274 %zext3 = zext i8 %phi3 to i3275 %or1 = or i32 %zext0, %zext176 %or2 = or i32 %or1, %zext277 %or3 = or i32 %or2, %zext378 ret i32 %or379}80 81define i32 @phi1UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {82; CHECK-LABEL: @phi1UndefInput(83; CHECK-NEXT: entry:84; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]85; CHECK: bb2:86; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 087; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 188; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 289; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 390; CHECK-NEXT: br label [[BB3]]91; CHECK: bb3:92; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 0, i8 undef>, [[ENTRY:%.*]] ]93; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])94; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3295; CHECK-NEXT: ret i32 [[TMP6]]96;97entry:98 br i1 %cond, label %bb2, label %bb399 100bb2:101 br label %bb3102 103bb3:104 %phi0 = phi i8 [ %arg0, %bb2 ], [ 0, %entry ]105 %phi1 = phi i8 [ %arg1, %bb2 ], [ 0, %entry ]106 %phi2 = phi i8 [ %arg2, %bb2 ], [ 0, %entry ]107 %phi3 = phi i8 [ %arg3, %bb2 ], [ undef, %entry ]108 %zext0 = zext i8 %phi0 to i32109 %zext1 = zext i8 %phi1 to i32110 %zext2 = zext i8 %phi2 to i32111 %zext3 = zext i8 %phi3 to i32112 %or1 = or i32 %zext0, %zext1113 %or2 = or i32 %or1, %zext2114 %or3 = or i32 %or2, %zext3115 ret i32 %or3116}117 118 119define i32 @phi1Undef1PoisonInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {120; CHECK-LABEL: @phi1Undef1PoisonInput(121; CHECK-NEXT: entry:122; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]123; CHECK: bb2:124; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 0125; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 1126; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2127; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3128; CHECK-NEXT: br label [[BB3]]129; CHECK: bb3:130; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 poison, i8 undef>, [[ENTRY:%.*]] ]131; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])132; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32133; CHECK-NEXT: ret i32 [[TMP6]]134;135entry:136 br i1 %cond, label %bb2, label %bb3137 138bb2:139 br label %bb3140 141bb3:142 %phi0 = phi i8 [ %arg0, %bb2 ], [ 0, %entry ]143 %phi1 = phi i8 [ %arg1, %bb2 ], [ 0, %entry ]144 %phi2 = phi i8 [ %arg2, %bb2 ], [ poison, %entry ]145 %phi3 = phi i8 [ %arg3, %bb2 ], [ undef, %entry ]146 %zext0 = zext i8 %phi0 to i32147 %zext1 = zext i8 %phi1 to i32148 %zext2 = zext i8 %phi2 to i32149 %zext3 = zext i8 %phi3 to i32150 %or1 = or i32 %zext0, %zext1151 %or2 = or i32 %or1, %zext2152 %or3 = or i32 %or2, %zext3153 ret i32 %or3154}155 156 157define i32 @phi1Undef2PoisonInputs(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {158; CHECK-LABEL: @phi1Undef2PoisonInputs(159; CHECK-NEXT: entry:160; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]161; CHECK: bb2:162; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i32 0163; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG0:%.*]], i32 1164; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2165; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3166; CHECK-NEXT: br label [[BB3]]167; CHECK: bb3:168; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 poison, i8 poison, i8 undef>, [[ENTRY:%.*]] ]169; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])170; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32171; CHECK-NEXT: ret i32 [[TMP6]]172;173entry:174 br i1 %cond, label %bb2, label %bb3175 176bb2:177 br label %bb3178 179bb3:180 %phi0 = phi i8 [ %arg0, %bb2 ], [ poison, %entry ]181 %phi1 = phi i8 [ %arg1, %bb2 ], [ 0, %entry ]182 %phi2 = phi i8 [ %arg2, %bb2 ], [ poison, %entry ]183 %phi3 = phi i8 [ %arg3, %bb2 ], [ undef, %entry ]184 %zext0 = zext i8 %phi0 to i32185 %zext1 = zext i8 %phi1 to i32186 %zext2 = zext i8 %phi2 to i32187 %zext3 = zext i8 %phi3 to i32188 %or1 = or i32 %zext0, %zext1189 %or2 = or i32 %or1, %zext2190 %or3 = or i32 %or2, %zext3191 ret i32 %or3192}193 194define i32 @phi1Undef1PoisonGapInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {195; CHECK-LABEL: @phi1Undef1PoisonGapInput(196; CHECK-NEXT: entry:197; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]198; CHECK: bb2:199; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i32 0200; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG3:%.*]], i32 1201; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG0:%.*]], i32 2202; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG2:%.*]], i32 3203; CHECK-NEXT: br label [[BB3]]204; CHECK: bb3:205; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 poison, i8 undef>, [[ENTRY:%.*]] ]206; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> [[TMP4]])207; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32208; CHECK-NEXT: ret i32 [[TMP6]]209;210entry:211 br i1 %cond, label %bb2, label %bb3212 213bb2:214 br label %bb3215 216bb3:217 %phi0 = phi i8 [ %arg0, %bb2 ], [ poison, %entry ]218 %phi1 = phi i8 [ %arg1, %bb2 ], [ 0, %entry ]219 %phi2 = phi i8 [ %arg2, %bb2 ], [ undef, %entry ]220 %phi3 = phi i8 [ %arg3, %bb2 ], [ 0, %entry ]221 %zext0 = zext i8 %phi0 to i32222 %zext1 = zext i8 %phi1 to i32223 %zext2 = zext i8 %phi2 to i32224 %zext3 = zext i8 %phi3 to i32225 %or1 = or i32 %zext0, %zext1226 %or2 = or i32 %or1, %zext2227 %or3 = or i32 %or2, %zext3228 ret i32 %or3229}230