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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5%struct.UFP = type { i32, i32, i32, [4 x i32] }6 7define void @test(ptr %u) {8; CHECK-LABEL: define void @test(9; CHECK-SAME: ptr [[U:%.*]]) {10; CHECK-NEXT: entry:11; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr null, align 412; CHECK-NEXT: [[IDX:%.*]] = getelementptr [[STRUCT_UFP:%.*]], ptr [[U]], i64 0, i32 3, i64 313; CHECK-NEXT: [[IDX1:%.*]] = getelementptr [[STRUCT_UFP]], ptr [[U]], i64 0, i32 3, i64 214; CHECK-NEXT: [[IDX2:%.*]] = load i32, ptr [[IDX]], align 415; CHECK-NEXT: [[IDX3:%.*]] = load i32, ptr [[IDX1]], align 416; CHECK-NEXT: br label [[WHILE:%.*]]17; CHECK: bb:18; CHECK-NEXT: store i32 [[OR_I_I:%.*]], ptr [[IDX]], align 419; CHECK-NEXT: store i32 [[OR19_I_I:%.*]], ptr [[IDX1]], align 420; CHECK-NEXT: ret void21; CHECK: while:22; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[OR26_I_I:%.*]], [[WHILE]] ]23; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[IDX3]], [[ENTRY]] ], [ [[OR19_I_I]], [[WHILE]] ]24; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[IDX2]], [[ENTRY]] ], [ 0, [[WHILE]] ]25; CHECK-NEXT: [[OR_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 0, i32 0)26; CHECK-NEXT: [[OR19_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 0)27; CHECK-NEXT: [[OR26_I_I]] = tail call i32 @llvm.fshl.i32(i32 0, i32 [[TMP1]], i32 0)28; CHECK-NEXT: br i1 false, label [[BB:%.*]], label [[WHILE]]29;30entry:31 %0 = load i32, ptr null, align 432 %idx = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 333 %idx1 = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 234 %idx2 = load i32, ptr %idx, align 435 %idx3 = load i32, ptr %idx1, align 436 br label %while37 38bb:39 store i32 %or.i.i, ptr %idx, align 440 store i32 %or19.i.i, ptr %idx1, align 441 ret void42 43while:44 %1 = phi i32 [ %0, %entry ], [ %or26.i.i, %while ]45 %2 = phi i32 [ %idx3, %entry ], [ %or19.i.i, %while ]46 %3 = phi i32 [ %idx2, %entry ], [ 0, %while ]47 %or.i.i = tail call i32 @llvm.fshl.i32(i32 %2, i32 0, i32 0)48 %or19.i.i = tail call i32 @llvm.fshl.i32(i32 %1, i32 %2, i32 0)49 %or26.i.i = tail call i32 @llvm.fshl.i32(i32 0, i32 %1, i32 0)50 br i1 false, label %bb, label %while51}52 53declare i32 @llvm.fshl.i32(i32, i32, i32)54