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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -S %s | FileCheck %s3 4declare float @memread(float) readonly nounwind willreturn #05declare <4 x float> @vmemread(<4 x float>)6 7define <4 x float> @memread_4x(ptr %a) {8; CHECK-LABEL: @memread_4x(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A:%.*]], align 1611; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @vmemread(<4 x float> [[TMP0]])12; CHECK-NEXT: ret <4 x float> [[TMP1]]13;14entry:15 %0 = load <4 x float>, ptr %a, align 1616 %vecext = extractelement <4 x float> %0, i32 017 %1 = tail call fast float @memread(float %vecext) #018 %vecins = insertelement <4 x float> poison, float %1, i32 019 %vecext.1 = extractelement <4 x float> %0, i32 120 %2 = tail call fast float @memread(float %vecext.1) #021 %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 122 %vecext.2 = extractelement <4 x float> %0, i32 223 %3 = tail call fast float @memread(float %vecext.2) #024 %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 225 %vecext.3 = extractelement <4 x float> %0, i32 326 %4 = tail call fast float @memread(float %vecext.3) #027 %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 328 ret <4 x float> %vecins.329}30 31declare float @memwrite(float) nounwind willreturn #132declare <4 x float> @vmemwrite(<4 x float>)33 34define <4 x float> @memwrite_4x(ptr %a) {35; CHECK-LABEL: @memwrite_4x(36; CHECK-NEXT: entry:37; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A:%.*]], align 1638; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 039; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR2:[0-9]+]]40; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 041; CHECK-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 142; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR2]]43; CHECK-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 144; CHECK-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 245; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR2]]46; CHECK-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 247; CHECK-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 348; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR2]]49; CHECK-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 350; CHECK-NEXT: ret <4 x float> [[VECINS_3]]51;52entry:53 %0 = load <4 x float>, ptr %a, align 1654 %vecext = extractelement <4 x float> %0, i32 055 %1 = tail call fast float @memwrite(float %vecext) #156 %vecins = insertelement <4 x float> poison, float %1, i32 057 %vecext.1 = extractelement <4 x float> %0, i32 158 %2 = tail call fast float @memwrite(float %vecext.1) #159 %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 160 %vecext.2 = extractelement <4 x float> %0, i32 261 %3 = tail call fast float @memwrite(float %vecext.2) #162 %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 263 %vecext.3 = extractelement <4 x float> %0, i32 364 %4 = tail call fast float @memwrite(float %vecext.3) #165 %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 366 ret <4 x float> %vecins.367}68 69attributes #0 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memread(vmemread)" }70attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memwrite(vmemwrite)" }71