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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}4 5define i32 @test(i32 %a, i8 %b, i8 %c) {6; CHECK-LABEL: define i32 @test(7; CHECK-SAME: i32 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {8; CHECK-NEXT: entry:9; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i32 010; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer11; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], <i8 -1, i8 -2, i8 -3, i8 -4>12; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 013; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer14; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>15; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i8> [[TMP4]] to <4 x i16>16; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <4 x i16> [[TMP8]], [[TMP9]]17; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i1> [[TMP5]] to i418; CHECK-NEXT: [[TMP11:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP10]])19; CHECK-NEXT: [[TMP7:%.*]] = zext i4 [[TMP11]] to i3220; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP7]], [[A]]21; CHECK-NEXT: ret i32 [[OP_RDX]]22;23entry:24 %0 = add i8 %c, -325 %dec19 = add i8 %c, -126 %conv20 = zext i8 %dec19 to i3227 %conv16.1 = sext i8 %b to i3228 %cmp17.1 = icmp sle i32 %conv20, %conv16.129 %conv18.1 = zext i1 %cmp17.1 to i3230 %a.1 = add nsw i32 %conv18.1, %a31 %dec19.1 = add i8 %c, -232 %conv20.1 = zext i8 %dec19.1 to i3233 %conv16.2 = sext i8 %b to i3234 %cmp17.2 = icmp sle i32 %conv20.1, %conv16.235 %conv18.2 = zext i1 %cmp17.2 to i3236 %a.2 = add nsw i32 %a.1, %conv18.237 %1 = zext i8 %0 to i3238 %conv16.158 = sext i8 %b to i3239 %cmp17.159 = icmp sle i32 %1, %conv16.15840 %conv18.160 = zext i1 %cmp17.159 to i3241 %a.161 = add nsw i32 %a.2, %conv18.16042 %dec19.162 = add i8 %c, -443 %conv20.163 = zext i8 %dec19.162 to i3244 %conv16.1.1 = sext i8 %b to i3245 %cmp17.1.1 = icmp sle i32 %conv20.163, %conv16.1.146 %conv18.1.1 = zext i1 %cmp17.1.1 to i3247 %a.1.1 = add nsw i32 %a.161, %conv18.1.148 ret i32 %a.1.149}50 51