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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG4 5target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"6 7define i8 @test1() {8; We fully promote these to the i24 load or store size, resulting in just masks9; and other operations that instcombine will fold, but no alloca. Note this is10; the same as test12 in basictest.ll, but here we assert big-endian byte11; ordering.12;13; CHECK-LABEL: @test1(14; CHECK-NEXT: entry:15; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i8 0 to i2416; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i24 undef, -25617; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]18; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 0 to i2419; CHECK-NEXT: [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i24 [[A_SROA_2_0_INSERT_EXT]], 820; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i24 [[A_SROA_3_0_INSERT_INSERT]], -6528121; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]]22; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i8 0 to i2423; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i24 [[A_SROA_0_0_INSERT_EXT]], 1624; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i24 [[A_SROA_2_0_INSERT_INSERT]], 6553525; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]26; CHECK-NEXT: [[B_SROA_0_0_EXTRACT_SHIFT:%.*]] = lshr i24 [[A_SROA_0_0_INSERT_INSERT]], 1627; CHECK-NEXT: [[B_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[B_SROA_0_0_EXTRACT_SHIFT]] to i828; CHECK-NEXT: [[B_SROA_2_0_EXTRACT_SHIFT:%.*]] = lshr i24 [[A_SROA_0_0_INSERT_INSERT]], 829; CHECK-NEXT: [[B_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[B_SROA_2_0_EXTRACT_SHIFT]] to i830; CHECK-NEXT: [[B_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[A_SROA_0_0_INSERT_INSERT]] to i831; CHECK-NEXT: [[BSUM0:%.*]] = add i8 [[B_SROA_0_0_EXTRACT_TRUNC]], [[B_SROA_2_0_EXTRACT_TRUNC]]32; CHECK-NEXT: [[BSUM1:%.*]] = add i8 [[BSUM0]], [[B_SROA_3_0_EXTRACT_TRUNC]]33; CHECK-NEXT: ret i8 [[BSUM1]]34;35entry:36 %a = alloca [3 x i8]37 %b = alloca [3 x i8]38 39 store i8 0, ptr %a40 %a1ptr = getelementptr [3 x i8], ptr %a, i64 0, i32 141 store i8 0, ptr %a1ptr42 %a2ptr = getelementptr [3 x i8], ptr %a, i64 0, i32 243 store i8 0, ptr %a2ptr44 %ai = load i24, ptr %a45 46 store i24 %ai, ptr %b47 %b0 = load i8, ptr %b48 %b1ptr = getelementptr [3 x i8], ptr %b, i64 0, i32 149 %b1 = load i8, ptr %b1ptr50 %b2ptr = getelementptr [3 x i8], ptr %b, i64 0, i32 251 %b2 = load i8, ptr %b2ptr52 53 %bsum0 = add i8 %b0, %b154 %bsum1 = add i8 %bsum0, %b255 ret i8 %bsum156}57 58define i64 @test2() {59; Test for various mixed sizes of integer loads and stores all getting60; promoted.61;62; CHECK-LABEL: @test2(63; CHECK-NEXT: entry:64; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_EXT:%.*]] = zext i8 1 to i4065; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_MASK:%.*]] = and i40 undef, -25666; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_4_0_INSERT_MASK]], [[A_SROA_2_SROA_4_0_INSERT_EXT]]67; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_EXT:%.*]] = zext i24 0 to i4068; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_SHIFT:%.*]] = shl i40 [[A_SROA_2_SROA_3_0_INSERT_EXT]], 869; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_MASK:%.*]] = and i40 [[A_SROA_2_SROA_4_0_INSERT_INSERT]], -429496704170; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_3_0_INSERT_MASK]], [[A_SROA_2_SROA_3_0_INSERT_SHIFT]]71; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_EXT:%.*]] = zext i8 0 to i4072; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_SHIFT:%.*]] = shl i40 [[A_SROA_2_SROA_0_0_INSERT_EXT]], 3273; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_MASK:%.*]] = and i40 [[A_SROA_2_SROA_3_0_INSERT_INSERT]], 429496729574; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_0_0_INSERT_MASK]], [[A_SROA_2_SROA_0_0_INSERT_SHIFT]]75; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i40 [[A_SROA_2_SROA_0_0_INSERT_INSERT]] to i5676; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i56 undef, -109951162777677; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i56 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_EXT]]78; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i16 1 to i5679; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i56 [[A_SROA_0_0_INSERT_EXT]], 4080; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i56 [[A_SROA_2_0_INSERT_INSERT]], 109951162777581; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i56 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]82; CHECK-NEXT: [[RET:%.*]] = zext i56 [[A_SROA_0_0_INSERT_INSERT]] to i6483; CHECK-NEXT: ret i64 [[RET]]84;85entry:86 %a = alloca [7 x i8]87 88 %a1ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 189 %a2ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 290 %a3ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 391 92 93 store i16 1, ptr %a94 95 store i8 1, ptr %a2ptr96 97 store i24 1, ptr %a3ptr98 99 store i40 1, ptr %a2ptr100 101; the alloca is splitted into multiple slices102; Here, i8 1 is for %a[6]103 104; Here, i24 0 is for %a[3] to %a[5]105 106; Here, i8 0 is for %a[2]107 108 109 110 %ai = load i56, ptr %a111 %ret = zext i56 %ai to i64112 ret i64 %ret113; Here, i16 1 is for %a[0] to %a[1]114}115 116define i64 @PR14132(i1 %flag) {117; Here we form a PHI-node by promoting the pointer alloca first, and then in118; order to promote the other two allocas, we speculate the load of the119; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8120; alloca. While this is a bit dubious, we were asserting on trying to121; rewrite it. The trick is that the code using the value may carefully take122; steps to only use the not-undef bits, and so we need to at least loosely123; support this. This test is particularly interesting because how we handle124; a load of an i64 from an i8 alloca is dependent on endianness.125; CHECK-LABEL: @PR14132(126; CHECK-NEXT: entry:127; CHECK-NEXT: br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]128; CHECK: if.then:129; CHECK-NEXT: [[B_0_LOAD_EXT:%.*]] = zext i8 1 to i64130; CHECK-NEXT: [[B_0_ENDIAN_SHIFT:%.*]] = shl i64 [[B_0_LOAD_EXT]], 56131; CHECK-NEXT: br label [[IF_END]]132; CHECK: if.end:133; CHECK-NEXT: [[PTR_0_SROA_SPECULATED:%.*]] = phi i64 [ [[B_0_ENDIAN_SHIFT]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ]134; CHECK-NEXT: ret i64 [[PTR_0_SROA_SPECULATED]]135;136entry:137 %a = alloca i64, align 8138 %b = alloca i8, align 8139 %ptr = alloca ptr, align 8140 141 store i64 0, ptr %a142 store i8 1, ptr %b143 store ptr %a, ptr %ptr144 br i1 %flag, label %if.then, label %if.end145 146if.then:147 store ptr %b, ptr %ptr148 br label %if.end149 150if.end:151 %tmp = load ptr, ptr %ptr152 %result = load i64, ptr %tmp153 154 ret i64 %result155}156 157declare void @f(i64 %x, i32 %y)158 159define void @test3() {160; This is a test that specifically exercises the big-endian lowering because it161; ends up splitting a 64-bit integer into two smaller integers and has a number162; of tricky aspects (the i24 type) that make that hard. Historically, SROA163; would miscompile this by either dropping a most significant byte or least164; significant byte due to shrinking the [4,8) slice to an i24, or by failing to165; move the bytes around correctly.166;167; The magical number 34494054408 is used because it has bits set in various168; bytes so that it is clear if those bytes fail to be propagated.169;170; If you're debugging this, rather than using the direct magical numbers, run171; the IR through '-sroa -instcombine'. With '-instcombine' these will be172; constant folded, and if the i64 doesn't round-trip correctly, you've found173; a bug!174;175; CHECK-LABEL: @test3(176; CHECK-NEXT: entry:177; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i32 134316040 to i64178; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i64 undef, -4294967296179; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]180; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i32 8 to i64181; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i64 [[A_SROA_0_0_INSERT_EXT]], 32182; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i64 [[A_SROA_3_0_INSERT_INSERT]], 4294967295183; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]184; CHECK-NEXT: call void @f(i64 [[A_SROA_0_0_INSERT_INSERT]], i32 8)185; CHECK-NEXT: ret void186;187entry:188 %a = alloca { i32, i24 }, align 4189 190 store i64 34494054408, ptr %a191 %tmp1 = load i64, ptr %a, align 4192 %tmp3 = load i32, ptr %a, align 4193 194 call void @f(i64 %tmp1, i32 %tmp3)195 ret void196}197 198define void @test4() {199; Much like @test3, this is specifically testing big-endian management of data.200; Also similarly, it uses constants with particular bits set to help track201; whether values are corrupted, and can be easily evaluated by running through202; -passes=instcombine to see that the i64 round-trips.203;204; CHECK-LABEL: @test4(205; CHECK-NEXT: entry:206; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_SHIFT:%.*]] = lshr i64 34494054408, 32207; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[A_SROA_0_0_EXTRACT_SHIFT]] to i32208; CHECK-NEXT: [[A_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i64 34494054408 to i32209; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i32 [[A_SROA_3_0_EXTRACT_TRUNC]] to i64210; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i64 undef, -4294967296211; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]212; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[A_SROA_0_0_EXTRACT_TRUNC]] to i64213; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i64 [[A_SROA_0_0_INSERT_EXT]], 32214; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i64 [[A_SROA_3_0_INSERT_INSERT]], 4294967295215; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]216; CHECK-NEXT: call void @f(i64 [[A_SROA_0_0_INSERT_INSERT]], i32 [[A_SROA_0_0_EXTRACT_TRUNC]])217; CHECK-NEXT: ret void218;219entry:220 %a = alloca { i32, i24 }, align 4221 %a2 = alloca i64, align 4222 223 store i64 34494054408, ptr %a2224 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %a, ptr align 4 %a2, i64 8, i1 false)225 226 %tmp3 = load i64, ptr %a, align 4227 %tmp5 = load i32, ptr %a, align 4228 229 call void @f(i64 %tmp3, i32 %tmp5)230 ret void231}232 233declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)234;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:235; CHECK-MODIFY-CFG: {{.*}}236; CHECK-PRESERVE-CFG: {{.*}}237