21 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s4 5; This test checks that SROA runs mem2reg on arrays of scalable vectors.6 7define [ 2 x <vscale x 4 x i32> ] @alloca(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {8; CHECK-LABEL: define [2 x <vscale x 4 x i32>] @alloca9; CHECK-SAME: (<vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) {10; CHECK-NEXT: [[AGG0:%.*]] = insertvalue [2 x <vscale x 4 x i32>] poison, <vscale x 4 x i32> [[X]], 011; CHECK-NEXT: [[AGG1:%.*]] = insertvalue [2 x <vscale x 4 x i32>] [[AGG0]], <vscale x 4 x i32> [[Y]], 112; CHECK-NEXT: ret [2 x <vscale x 4 x i32>] [[AGG1]]13;14 %addr = alloca [ 2 x <vscale x 4 x i32> ], align 415 %agg0 = insertvalue [ 2 x <vscale x 4 x i32> ] poison, <vscale x 4 x i32> %x, 016 %agg1 = insertvalue [ 2 x <vscale x 4 x i32> ] %agg0, <vscale x 4 x i32> %y, 117 store [ 2 x <vscale x 4 x i32> ] %agg1, ptr %addr, align 418 %val = load [ 2 x <vscale x 4 x i32> ], ptr %addr, align 419 ret [ 2 x <vscale x 4 x i32> ] %val20}21